MC68332ACEH16 Datasheet, PDF (75/88 Pages) Freescale Semiconductor, Inc – 32-Bit Modular Microcontroller

Freescale Semiconductor, Inc.
SPCR2 — QSPI Control Register 2
$YFFC1C
15
14
13
12
11
8
7
6
5
4
3
0
SPIFIE WREN WRTO 0
ENDQP
0
0
0
0
NEWQP
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SPCR2 contains QSPI configuration parameters. The CPU can read and write this register; the QSM
has read access only. Writes to SPCR2 are buffered. A write to SPCR2 that changes a bit value while
the QSPI is operating is ineffective on the current serial transfer, but becomes effective on the next se-
rial transfer. Reads of SPCR2 return the current value of the register, not of the buffer.
SPIFIE — SPI Finished Interrupt Enable
0 = QSPI interrupts disabled
1 = QSPI interrupts enabled
SPIFIE enables the QSPI to generate a CPU interrupt upon assertion of the status flag SPIF.
WREN — Wrap Enable
0 = Wraparound mode disabled
1 = Wraparound mode enabled
WREN enables or disables wraparound mode.
WRTO — Wrap To
When wraparound mode is enabled, after the end of queue has been reached, WRTO determines
which address the QSPI executes.
Bit 12 — Not Implemented
ENDQP — Ending Queue Pointer
This field contains the last QSPI queue address.
Bits [7:4] — Not Implemented
NEWQP — New Queue Pointer Value
This field contains the first QSPI queue address.
SPCR3 — QSPI Control Register 3
$YFFC1E
15
14
13
12
11
10
9
8
7
0
0
0
0
0
0 LOOPQ HMIE HALT
SPSR
RESET:
0
0
0
0
0
0
0
0
SPCR3 contains QSPI configuration parameters. The CPU can read and write SPCR3, but the QSM
has read-only access.
Bits [15:11] — Not Implemented
LOOPQ — QSPI Loop Mode
0 = Feedback path disabled
1 = Feedback path enabled
LOOPQ controls feedback on the data serializer for testing.
HMIE — HALTA and MODF Interrupt Enable
0 = HALTA and MODF interrupts disabled
1 = HALTA and MODF interrupts enabled
HMIE controls CPU interrupts caused by the HALTA status flag or the MODF status flag in SPSR.
MC68332
MC68332TS/D
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MOTOROLA
75