MC68332ACEH16 Datasheet, PDF (30/88 Pages) Freescale Semiconductor, Inc – 32-Bit Modular Microcontroller

Freescale Semiconductor, Inc.
Chip-select assertion can be synchronized with bus control signals to provide output enable, read/write
strobes, or interrupt acknowledge signals. Logic can also generate DSACK signals internally. A single
DSACK generator is shared by all circuits. Multiple chip selects assigned to the same address and con-
trol must have the same number of wait states.
Chip selects can also be synchronized with the ECLK signal available on ADDR23.
When a memory access occurs, chip-select logic compares address space type, address, type of ac-
cess, transfer size, and interrupt priority (in the case of interrupt acknowledge) to parameters stored in
chip-select registers. If all parameters match, the appropriate chip-select signal is asserted. Select sig-
nals are active low. Refer to the following block diagram of a single chip-select circuit.
INTERNAL
SIGNALS
ADDRESS
BUS CONTROL
BASE ADDRESS REGISTER
ADDRESS COMPARATOR
OPTION COMPARE
OPTION REGISTER
TIMING
AND
PIN
CONTROL
AVEC
DSACK
AVEC
GENERATOR
DSACK
GENERATOR
PIN
ASSIGNMENT
REGISTER
PIN
DATA
REGISTER
Figure 9 Chip-Select Circuit Block Diagram
CHIP SEL BLOCK
The following table lists allocation of chip-selects and discrete outputs on the pins of the MCU.
Pin
CSBOOT
BR
BG
BGACK
FC0
FC1
FC2
ADDR19
ADDR20
ADDR21
ADDR22
ADDR23
Chip Select
CSBOOT
CS0
CS1
CS2
CS3
CS4
CS5
CS6
CS7
CS8
CS9
CS10
Discrete Outputs
—
—
—
—
PC0
PC1
PC2
PC3
PC4
PC5
PC6
ECLK
MOTOROLA
30
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MC68332
MC68332TS/D