K51P100M72SF1 Datasheet, PDF (75/77 Pages) Freescale Semiconductor, Inc – K51 Sub-Family

Revision History
1
A
PTD7
2
3
4
5
6
PTD5
PTD4/
LLWU_P14
PTC19
PTC14
PTC13
7
8
9
PTC8
PTC4/
LLWU_P8
VLL1
10
VLL2
11
VLL3
A
B
NC
PTD6/
LLWU_P15
PTD3
PTC18
NC
PTC12
PTC7
PTC3/
LLWU_P7
PTC0
PTB16
VCAP2 B
C
NC
NC
PTD2/
LLWU_P13
PTC17
PTC11/
LLWU_P11
PTC10
PTC6/
LLWU_P10
PTC2
PTB19
PTB11
VCAP1 C
D
NC
NC
PTD1
PTD0/
LLWU_P12
PTC16
PTC9
PTC5/
PTC1/
LLWU_P9 LLWU_P6
PTB18
PTB10
PTB8
D
E
NC
PTE2/
PTE1/
LLWU_P1 LLWU_P0
PTE0
VDD
VDD
VDD
PTB23
PTB17
PTB9
PTB7
E
F USB0_DP USB0_DM
NC
PTE3
VDDA
VSSA
VSS
PTB22
PTB21
PTB20
NC
F
G VOUT33 VREGIN
VSS
PTE5
VREFH VREFL
VSS
PTB3
PTB2
ADC0_SE16/
OP0_OUT/
H
ADC0_DP1/ ADC0_DM1/ CMP1_IN2/
OP0_DP0 OP0_DM0 ADC0_SE21/
TRI0_DM
OP0_DP1/
OP1_DP1
ADC1_SE16/
J
ADC1_DP1/
OP1_DP0/
OP1_DM1
OP1_OUT/
ADC1_DM1/ CMP2_IN2/
OP1_DM0 ADC0_SE22/
OP0_DP2/
TRI0_DP
OP1_DP2
NC
CMP2_IN5/ PTE4/
ADC1_SE22 LLWU_P2
PTA1
NC
PTA0
PTA2
PTA4/
LLWU_P3
CMP0_IN4/ DAC0_OUT/
K
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
TRI0_OUT/
OP1_DM2
CMP2_IN3/ CMP1_IN3/
ADC1_SE23/ADC0_SE23/
OP0_DP5/ OP0_DP4/
VBAT
OP1_DP5 OP1_DP4
NC
PTA12
PTA3
NC
PTA14
L
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
XTAL32
EXTAL32
VSS
RTC_
PTA13/
WAKEUP_B LLWU_P4
PTA15
1
2
3
4
5
6
7
8
9
PTB1
PTB0/
LLWU_P5
G
NC
NC
H
NC
RESET_b J
VSS
PTA19 K
VDD
PTA18 L
10
11
Figure 28. K51 104 MAPBGA Pinout Diagram
9 Revision History
The following table provides a revision history for this document.
Table 52. Revision History
Rev. No.
1
Date
3/2012
Substantial Changes
Initial public release
Table continues on the next page...
K51 Sub-Family Data Sheet, Rev. 2, 4/2012.
Freescale Semiconductor, Inc.
75