MSE9S08QG8 Datasheet, PDF (7/8 Pages) Freescale Semiconductor, Inc – Mask Set Errata for Mask 3M77B

Case 5: Center-Aligned PWM
TPMxCnVH:TPMxCnVL Changed from 0x0000 to a Non-Zero Value
Description
This case occurs only while the counter is counting down (first half of the center-aligned PWM period) and
then TPMxCnVH:TPMxCnVL is changed back to 0x0000 during the first half of the next PWM period
(while the counter is counting down). This is a very unlikely case in any practical application. The PWM
output changes to the active level at the middle of the first PWM period as the count reaches 0x0000
instead of waiting for the start of a new PWM period to begin using the new duty cycle setting, and then
the output remains active until the end of the second PWM period. In this very unusual case, the PWM
output remains active for one and one-half PWM periods rather than remaining inactive for the first PWM
period and then active for 2 × TPMxCnVH:TPMxCnVL during the next PWM period.
Workaround
Use a negative channel value instead of 0x0000 to produce 0% duty cycle. This can be done by checking
any value that is about to be written to the channel value registers, and then decrementing the 16-bit value
or the high-order byte of this value before writing it to the channel value registers. This produces the
desired 0% duty cycle and it avoids the problems related to a zero in the channel value registers.
Case 6: Edge-Aligned PWM
TPMxCnVH:TPMxCnVL Changed from 0x0000 to a Non-Zero Value
Description
This is a minor issue related to edge-aligned PWM when duty cycle is changed from 0x0000 to a non-
zero value. This issue is a specification clarification rather than a design error.
In this case, the channel value update occurs at the same time as the new PWM period begins, but due
to circuit delays, the update occurs slightly too late for the new duty cycle to take effect for that PWM
period and an extra period of 0% duty cycle is produced. This causes the new PWM duty cycle to take
effect one PWM period later than expected. This should not cause any application problems so the data
book functional description will be changed to clarify this situation.
Case 7: Changing the Counter Prescaler while the TPM Counter Is Disabled
Description
This case would not arise in most applications because it would be unusual to change the prescaler at
any time other than initial timer setup after reset.
1. TPM counter was previously running
2. Counting is stopped by writing 0:0 to CLKS[1:0]
3. Change prescale value PS[2:1:0] to a different value while keeping clocks off (CLKS[1:0] = 0:0)
4. Clear the counter by writing any value to TPMxCNTH:TPMxCNTL
Mask Set Errata for 9S08QG8, Mask 3M77B
Freescale Semiconductor
7