MSE9S08QG8 Datasheet, PDF (4/8 Pages) Freescale Semiconductor, Inc – Mask Set Errata for Mask 3M77B

values occur twice (once during the down-counting phase and again during the up-counting phase).
Therefore, the total period of the PWM signal is two times the value in TPMMODH:TPMMODL.
The value on each TPM timer output pin is controlled by an internal flip-flop that is cleared at reset but is
not readable by software. These internal flip-flops change state when timer output compare events or
PWM duty cycle compare events occur (when the channel value registers match the timer count
registers). This leads to these outputs remaining in a previous state until a compare event occurs after
changing the configuration of the timer system. When the timer is initialized the first time after a reset, the
state of these output flip-flops is known to be reset (logic low). If the configuration is changed after the
channel has been running in another configuration for some period of time, you sometimes do not know
the state of these internal flip-flops (and therefore the state of the timer output pins) until a new channel
value register compare event occurs. There is nothing improper about these periods before the first event
occurs, however some users might be surprised the first time they notice this behavior.
When the MCU is reset, the count (TPMCNTH:TPMCNTL) is reset to 0x0000. If the timer is configured
for center-aligned pulse-width modulation (PWM) and then the clock is started, this corresponds to the
middle of a PWM period. If the internal flip-flop corresponding to the output was at the inactive level when
the PWM started, this would appear as if there was an extra half period of delay before the first full PWM
cycle started. If the internal flip-flop corresponding to the output happened to be at the active level when
this PWM was started, a pulse equivalent to half of a normal duty cycle pulse could be produced at the
PWM output pin.
There are eight cases discussed in this errata:
• Cases 1 and 2 — These are two error cases near the 100% duty cycle boundary. The first is when
the channel value registers are set equal to the modulo value. The second is when the channel
value registers are set to one less than the modulo value.
• Cases 3, 4, and 5 — These cases are related to changing the channel value to or from 0x0000.
The errors depend upon whether this is done during the first or second half of the center-aligned
PWM period. In all of these cases, the workaround strategy is to produce 0% duty cycle with a
negative channel value instead of using the 0x0000 value. This can be done by checking any value
that is about to be written to the channel value registers, and then decrement the 16-bit value or
the high-order byte of the value before writing it to the channel value registers. This produces the
desired 0% duty cycle and avoids the problems related to a zero in the channel value registers.
• Case 6 — Although this behavior wasn’t discussed in the data sheet, the operation is different than
some users might expect. In edge-aligned PWM mode, when the channel value is changed from
zero to a non-zero value, the new PWM settings can take an extra half PWM period to take effect.
It is unlikely that this would cause any problems in any practical application system.
• Case 7 — This case is more of a clarification of an unusual situation rather than a design problem.
This case happens when the prescale factor is changed during operation and only affects center-
aligned PWM. It would be very unusual to change the prescale setting after it is set during reset
initialization. The prescale flip-flops are not reset when the prescale setting is changed, so the first
prescaled clock period after a change may be shorter or longer than expected.
• Case 8 — This case would only arise when a series of unlikely events happened to occur. It affects
only center-aligned PWM mode if the timer counter is stopped, reset, and restarted when the count
value happened to be equal to the TPMxMODH:TPMxMODL value. Because the timer counter
would not normally be stopped during operation in center-aligned PWM mode, this case should
never arise in a practical application.
Mask Set Errata for 9S08QG8, Mask 3M77B
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Freescale Semiconductor