MSE9S08QG8 Datasheet, PDF (5/8 Pages) Freescale Semiconductor, Inc – Mask Set Errata for Mask 3M77B

Case 1: Center-Aligned PWM
Channel Value (TPMxCnVH:TPMxCnVL) = Modulo Value (TPMxMODH:TPMxMODL)
Description
This should produce 100% duty cycle where the TPM output pin remains at the active level continuously.
Instead, the output remains at the inactive level, which corresponds to 0% duty cycle.
Workarounds
Check any value that is about to be written to the channel value registers. If the value is the same as the
modulo value, increment the value before writing it to the channel value register. This workaround will
work for any modulo value that is greater than zero and less than 0x7FFF. Setting the channel value to
any 2’s complement negative value (0x8000 through 0xFFFF) results in 0% duty cycle as expected and
described in the original TPM documentation.
Another workaround would be to choose not to use 100% duty cycle in the application. Not all applications
require the range to include the 100% duty cycle case.
Case 2: Center-Aligned PWM
Channel Value (TPMxCnVH:TPMxCnVL) = Modulo Value Minus 1 (TPMxMODH:TPMxMODL – 1)
Description
This should produce almost 100% duty cycle where the TPM output pin remains at the active level for
[(TPMxCnVH:TPMxCnVL × 100)/(TPMxMODH:TPMxMODL)]% of the period. Instead, the output
remains at the inactive level which corresponds to 0% duty cycle.
Workarounds
Reduce the prescale factor by a factor of two and then multiply the modulo and channel value settings by
a factor of two. In this way, the frequency and resolution of the PWM output remain the same but channel
values are always even numbers and are never equal to the modulo setting minus one.
Consider the case of a 20-MHz bus frequency, 25-kHz PWM frequency, and 0.25% resolution on the duty
cycle. Before making the adjustments suggested in this workaround, you could have the following setup:
Set the modulo to 400 and the prescale factor in PS2:PS1:PS0 to divide by 2 (0:0:1). Each step of the
channel value from 0–1–2…398–399–400 would increase the duty cycle by 0.25%.
Increasing the modulo value to 800 and reducing the prescale factor to divide-by one, would still produce
the same period or PWM frequency. If the original channel values were multiplied by two (shift left one bit
position) before writing them to the channel value register, the resolution would still be 0.25% per step of
the channel value, but the channel values would step by 2 each time as in 0-2-4-6…796-798-800. With
this workaround, the channel value would never be equal to the modulo value minus one, and the error
condition would not arise.
Mask Set Errata for 9S08QG8, Mask 3M77B
Freescale Semiconductor
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