MC9RS08LE4CWL Datasheet, PDF(7/28 Page) Freescale Semiconductor, Inc – Up to 20 MHz CPU at 2.7 V to 5.5 V across temperature range of

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MC9RS08LE4CWL Datasheet, PDF (7/28 Pages) Freescale Semiconductor, Inc – Up to 20 MHz CPU at 2.7 V to 5.5 V across temperature range of –40°C to 85°C

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ESD Protection and Latch-Up Immunity

Table 4. Thermal Characteristics

Rating

Operating temperature range (packaged)

Maximum junction temperature

Thermal resistance

Single layer board 28-pin SOIC

Symbol

TJMAX

Î¸JA

Value

TL to TH

â40 to 85

105

Unit

Â°C

Â°C/W

The average chip-junction temperature (TJ) in Â°C can be obtained from:

TJ = TA + (PD Ã Î¸JA)

Eqn. 1

where:

TA = Ambient temperature, Â°C

Î¸JA = Package thermal resistance, junction-to-ambient, Â°C /W

PD = Pint + PI/O

Pint = IDD Ã VDD, Watts chip internal power

PI/O = Power dissipation on input and output pins user determined

For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ

(if PI/O is neglected) is:

PD = K Ã· (TJ + 273Â°C)

Solving Equation 1 and Equation 2 for K gives:

Eqn. 2

K = PD Ã (TA + 273Â°C) + Î¸JAÃ (PD)2

Eqn. 3

where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring

PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by

solving equations 1 and 2 iteratively for any value of TA.

3.5 ESD Protection and Latch-Up Immunity

Although damage from electrostatic discharge (ESD) is much less common on these devices than on early

CMOS circuits, normal handling precautions must be used to avoid exposure to static discharge.

Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels

of static without suffering any permanent damage.

All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade

Integrated Circuits. During the device qualification ESD stresses were performed for the human body

model (HBM), the machine model (MM) and the charge device model (CDM).

A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device

specification. Complete DC parametric and functional testing is performed per the applicable device

MC9RS08LE4 MCU Data Sheet, Rev. 3

Freescale Semiconductor

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