MC9RS08LE4CWL Datasheet, PDF (17/28 Pages) Freescale Semiconductor, Inc – Up to 20 MHz CPU at 2.7 V to 5.5 V across temperature range of –40°C to 85°C

Internal Clock Source (ICS) Characteristics
3.9 Internal Clock Source (ICS) Characteristics
Table 10. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient)
Num C
Characteristic
Symbol
Min
Typical¹
Max
Unit
Square wave input clock frequency (EREFS = 0)
1C
FLL bypass external (CLKS = 10)
FLL engaged external (CLKS = 00)
f_extal
0
—
0.03125
—
20
MHz
5
2 C Average internal reference frequency - untrimmed
f_{int_ut}
25
3 C Average internal reference frequency - trimmed
f_{int_t}
31.25
4 C DCO output frequency range — untrimmed
f_{dco_ut}
12.8
5 C DCO output frequency range — trimmed
f_{dco_t}
16
6
C
Resolution of trimmed DCO output frequency at
fixed voltage and temperature
Δf_{dco_res_t}
—
31.25
31.25
16
16
—
41.66
39.0625
21.33
20
kHz
kHz
MHz
MHz
±0.2 %f_dco
7
C
Total deviation of trimmed DCO output frequency
over voltage and temperature
Δf_{dco_t}
—
—
±2
%f_dco
8 C FLL acquisition time ^3,2
t_acquire
—
—
1
ms
9
C
Long term Jitter ³ of DCO output clock (averaged
over 2 ms interval)
C_Jitter
—
—
0.6
%f_dco
1 _{Data in Typical column was characterized at 3.0 V, 25 °C or is typical recommended value.}
2 _{This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or}
changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as
the reference, this specification assumes it is already running.
3 _{Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBUS.}
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via V_DD and V_SS and variation in crystal oscillator frequency increase the C_Jitter percentage
for a given interval.
3.10 AC Characteristics
This section describes AC timing characteristics for each peripheral system.
3.10.1 Control Timing
Table 11. Control Timing
Num C
Parameter
Symbol
Min
Typical
Max
Unit
1
D Bus frequency (t_cyc = 1/f_Bus)
f_Bus
0
—
10
MHz
2
D Real time interrupt internal oscillator period
t_RTI
700
1000
3
D External RESET pulse width¹
t_extrst
150
—
4
D KBI pulse width²
t_KBIPW
1.5 t_cyc
—
5
D KBI pulse width in stop¹
t_KBIPWS
100
—
6
C Port rise and fall time (load = 50 pF)³
Slew rate control disabled (PTxSE = 0) t_Rise, t_Fall
—
11
Slew rate control enabled (PTxSE = 1)
—
35
1300
μs
—
ns
—
ns
—
ns
—
ns
—
1 _{This is the shortest pulse that is guaranteed to pass through the pin input filter circuitry. Shorter pulses may or may not be}
recognized.
MC9RS08LE4 MCU Data Sheet, Rev. 3
Freescale Semiconductor
17