33886_07 Datasheet, PDF (7/25 Pages) Freescale Semiconductor, Inc – 5.0 A H-Bridge

ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 5.0 V ≤ V+ ≤ 28 V and -40°C ≤ T_A ≤ 125°C unless otherwise noted. Typical values noted
reflect the approximate parameter mean at T_A = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
TIMING CHARACTERISTICS
PWM Frequency ⁽²¹⁾
Maximum Switching Frequency During Active Current Limiting ⁽²²⁾
Output ON Delay ⁽²³⁾
V+ = 14 V
Output OFF Delay ⁽²³⁾
V+ = 14 V
Output Rise and Fall Time ⁽²⁴⁾
V+ = 14 V, I_OUT = 3.0 A
f _PWM
–
f _MAX
–
t _{d (ON)}
–
–
10
kHz
–
20
kHz
µs
–
18
t _{d (OFF)}
–
µs
–
18
t_f, t_r
µs
2.0
5.0
8.0
Output Latch-OFF Time
Output Blanking Time
Output FET Body Diode Reverse Recovery Time ⁽²⁵⁾
Disable Delay Time ⁽²⁶⁾
Short Circuit / Overtemperature Turn-OFF Time ⁽²⁷⁾
Power-OFF Delay Time
t_a
15
t_b
12
t_rr
100
t _{d (disable)}
–
t _FAULT
–
t _pod
–
20.5
16.5
–
–
4.0
1.0
26
µs
21
µs
–
ns
8.0
µs
–
µs
5.0
ms
Notes
21. The outputs can be PWM controlled from an external source. This is typically done by holding one input high while applying a PWM
pulse train to the other input. The maximum PWM frequency obtainable is a compromise between switching losses and switching
frequency. Refer to Typical Switching Waveforms, Figures 10 through 17, pp. 10–11.
22. The Maximum Switching Frequency during active current limiting is internally implemented. The internal control produces a constant
OFF-time PWM of the output. The output load current effects the Maximum Switching Frequency.
23. Output Delay is the time duration from the midpoint of the IN1 or IN2 input signal to the 10% or 90% point (dependent on the transition
direction) of the OUT1 or OUT2 signal. If the output is transitioning High-to-Low, the delay is from the midpoint of the input signal to the
90% point of the output response signal. If the output is transitioning Low-to-High, the delay is from the midpoint of the input signal to
the 10% point of the output response signal. See Figure 4, page 8.
24. Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal. See Figure 6, page 8.
25. Parameter is guaranteed by design but not production tested.
26. Disable Delay Time is the time duration from the midpoint of the D (disable) input signal to 10% of the output tri-state response. See
Figure 5, page 8.
27. Increasing currents will become limited at I_LIM. Hard shorts will breach the I_SCH or I_SCL limit, forcing the output into an immediate tri-
state latch-OFF. See Figures 8 and 9, page 9. Active current limiting will cause junction temperatures to rise. A junction temperature
above 160°C will cause the active current limiting to progressively “fold-back” (or decrease) to 2.5 A typical at 175°C where thermal
latch-OFF will occur. See Figure 7, page 8.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33886
7