MC68HC08JL3_05 Datasheet, PDF (67/198 Pages) Freescale Semiconductor, Inc – Microcontrollers

STOP/WAIT
CONTROL
SIM
COUNTER
VDD
INTERNAL
PULL-UP
÷2
CLOCK
CONTROL
CLOCK GENERATORS
RESET
PIN LOGIC
POR CONTROL
RESET PIN CONTROL
SIM RESET STATUS REGISTER
MASTER
RESET
CONTROL
RESET
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO OSCILLATOR)
COP CLOCK
2OSCOUT (FROM OSCILLATOR)
OSCOUT (FROM OSCILLATOR)
INTERNAL CLOCKS
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP TIMEOUT (FROM COP MODULE)
USB RESET (FROM USB MODULE)
INTERRUPT CONTROL
AND PRIORITY DECODE
INTERRUPT SOURCES
CPU INTERFACE
Figure 7-1. SIM Block Diagram
Signal Name
2OSCOUT
OSCOUT
IAB
IDB
PORRST
IRST
R/W
Table 7-1. Signal Name Conventions
Description
Buffered clock from the X-tal oscillator circuit or the RC oscillator circuit.
The 2OSCOUT frequency divided by two. This signal is again divided by two in the
SIM to generate the internal bus clocks. (Bus clock = 2OSCOUT ÷ 4)
Internal address bus
Internal data bus
Signal from the power-on reset module to the SIM
Internal reset signal
Read/write signal
MC68H(R)C08JL3 — Rev. 4.1
Freescale Semiconductor
Technical Data
67