MC68HC08JL3_05 Datasheet, PDF (146/198 Pages) Freescale Semiconductor, Inc – Microcontrollers

12.5.2 Data Direction Register D (DDRD)
Data direction register D determines whether each port D pin is an input
or an output. Writing a logic one to a DDRD bit enables the output buffer
for the corresponding port D pin; a logic zero disables the output buffer.
Address: $0007
Bit 7
Read:
DDRD7
Write:
Reset: 0
6
DDRD6
0
5
DDRD5
0
4
DDRD4
0
3
DDRD3
0
2
DDRD2
0
1
DDRD1
0
Bit 0
DDRD0
0
Figure 12-10. Data Direction Register D (DDRD)
DDRD[7:0] — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears
DDRD[7:0], configuring all port D pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
NOTE:
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1. Figure 12-11 shows
the port D I/O logic.
READ DDRD ($0007)
WRITE DDRD ($0007)
RESET
WRITE PTD ($0003)
DDRDx
PTDx
PTDPU[6:7]
5k
PTDx
READ PTD ($0003)
Technical Data
146
PTD[0:3] To Analog-To-Digital Converter
PTD[4:5] To Timer
Figure 12-11. Port D I/O Circuit
MC68H(R)C08JL3 — Rev. 4.1
Freescale Semiconductor