MC68HC08JL3_05 Datasheet, PDF (43/198 Pages) Freescale Semiconductor, Inc – Microcontrollers

Address: $001F
Bit 7
6
5
4
3
2
1
Read:
COPRS
R
Write:
Reset: 0
0
R
LVID
R
SSREC STOP
0
0
0
0
0
R = Reserved
Figure 5-2. Configuration Register 1 (CONFIG1)
Bit 0
COPD
0
COPRS —þCOP reset period selection bit
1 = COP reset cycle = (2¹³ – 2⁴) × 2OSCOUT
0 = COP reset cycle = (2¹⁸ – 2⁴) × 2OSCOUT
LVID —þLow Voltage Inhibit Disable Bit
1 = Low Voltage Inhibit disabled
0 = Low Voltage Inhibit enabled
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of
32 × OSCXCLK cycles instead of a 4096 × 2OSCOUT cycle delay.
1 = Stop mode recovery after 32 × 2OSCOUT cycles
0 = Stop mode recovery after 4096 × 2OSCOUT cycles
NOTE: Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal, do not set the SSREC bit.
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. (See Section 15. Computer
Operating Properly (COP).)
1 = COP module disabled
0 = COP module enabled
MC68H(R)C08JL3 — Rev. 4.1
Freescale Semiconductor
Technical Data
43