K52P144M100SF2 Datasheet, PDF (67/75 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz

144 144 Pin Name Default
ALT0
ALT1
LQF MAP
P BGA
39 L4 TRI0_DM TRI0_DM TRI0_DM
40 M4 TRI0_DP TRI0_DP TRI0_DP
41 L5 TRI1_DM TRI1_DM TRI1_DM
42 M5 TRI1_DP TRI1_DP TRI1_DP
43 K5 TRI1_OUT/ TRI1_OUT TRI1_OUT/
CMP2_IN5/
CMP2_IN5/
ADC1_SE2
ADC1_SE2
2
2
44 K4 DAC0_OUT/ DAC0_OUT DAC0_OUT/
CMP1_IN3/
CMP1_IN3/
ADC0_SE2
ADC0_SE2
3/OP0_DP4/
3/OP0_DP4/
OP1_DP4
OP1_DP4
45 J4 DAC1_OUT/ DAC1_OUT DAC1_OUT/
CMP2_IN3/
CMP2_IN3/
ADC1_SE2
ADC1_SE2
3/OP0_DP5/
3/OP0_DP5/
OP1_DP5
OP1_DP5
46 M7 XTAL32 XTAL32 XTAL32
47 M6 EXTAL32 EXTAL32 EXTAL32
48 L6 VBAT
VBAT
VBAT
49 H4 PTE28
DISABLED
PTE28
50 J5 PTA0
JTAG_TCL TSI0_CH1 PTA0
K/
SWD_CLK/
EZP_CLK
51 J6 PTA1
JTAG_TDI/ TSI0_CH2 PTA1
EZP_DI
52 K6 PTA2
JTAG_TDO/ TSI0_CH3 PTA2
TRACE_SW
O/EZP_DO
53 K7 PTA3
JTAG_TMS/ TSI0_CH4 PTA3
SWD_DIO
54 L7 PTA4
NMI_b/ TSI0_CH5 PTA4
EZP_CS_b
55 M8 PTA5
DISABLED
PTA5
56 E7 VDD
57 G7 VSS
58 J7 PTA6
59 J8 PTA7
60 K8 PTA8
61 L8 PTA9
VDD
VDD
VSS
VSS
DISABLED
PTA6
ADC0_SE1 ADC0_SE1 PTA7
0
0
ADC0_SE1 ADC0_SE1 PTA8
1
1
DISABLED
PTA9
Pinout
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
UART0_CT FTM0_CH5
S_b
JTAG_TCL EZP_CLK
K/
SWD_CLK
UART0_RX FTM0_CH6
JTAG_TDI EZP_DI
UART0_TX FTM0_CH7
UART0_RT
S_b
FTM0_CH0
FTM0_CH1
JTAG_TDO/ EZP_DO
TRACE_SW
O
JTAG_TMS/
SWD_DIO
NMI_b
EZP_CS_b
FTM0_CH2 RMII0_RXE CMP2_OUT I2S0_RX_B JTAG_TRS
R/
CLK
T
MII0_RXER
FTM0_CH3
FTM0_CH4
FTM1_CH0
FTM1_CH1 MII0_RXD3
TRACE_CL
KOUT
TRACE_D3
FTM1_QD_
PHA
FTM1_QD_
PHB
TRACE_D2
TRACE_D1
K52 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
67