K52P144M100SF2 Datasheet, PDF (54/75 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz

Peripheral operating requirements and behaviors
6.8 Communication interfaces
6.8.1 Ethernet switching specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
6.8.1.1 MII signal switching specifications
The following timing specs meet the requirements for MII style interfaces for a range of
transceiver devices.
Table 40. MII signal switching specifications
Symbol
—
MII1
Description
RXCLK frequency
RXCLK pulse width high
MII2
RXCLK pulse width low
MII3
RXD[3:0], RXDV, RXER to RXCLK setup
MII4
RXCLK to RXD[3:0], RXDV, RXER hold
—
TXCLK frequency
MII5
TXCLK pulse width high
MII6
TXCLK pulse width low
MII7
TXCLK to TXD[3:0], TXEN, TXER invalid
MII8
TXCLK to TXD[3:0], TXEN, TXER valid
Min.
—
35%
35%
5
5
—
35%
35%
2
—
Max.
25
65%
65%
—
—
25
65%
65%
—
25
Unit
MHz
RXCLK
period
RXCLK
period
ns
ns
MHz
TXCLK
period
TXCLK
period
ns
ns
K52 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
54
Preliminary
Freescale Semiconductor, Inc.