K20P81M100SF2V2 Datasheet, PDF (66/71 Pages) Freescale Semiconductor, Inc – K20 Sub-Family

Pinout
8.1 K20 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
80 Pin Name
LQFP
1 PTE0
2 PTE1/
LLWU_P0
3 PTE2/
LLWU_P1
4 PTE3
5 PTE4/
LLWU_P2
6 PTE5
7 VDD
8 VSS
9 USB0_DP
10 USB0_DM
11 VOUT33
12 VREGIN
13 PGA0_DP/
ADC0_DP0/
ADC1_DP3
14 PGA0_DM/
ADC0_DM0/
ADC1_DM3
15 PGA1_DP/
ADC1_DP0/
ADC0_DP3
16 PGA1_DM/
ADC1_DM0/
ADC0_DM3
17 VDDA
18 VREFH
19 VREFL
20 VSSA
21 VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
22 DAC0_OUT/
CMP1_IN3/
ADC0_SE23
23 XTAL32
24 EXTAL32
Default
ADC1_SE4a
ADC1_SE5a
ADC1_SE6a
ADC1_SE7a
DISABLED
DISABLED
VDD
VSS
USB0_DP
USB0_DM
VOUT33
VREGIN
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
VDDA
VREFH
VREFL
VSSA
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
XTAL32
EXTAL32
ALT0
ADC1_SE4a
ADC1_SE5a
ADC1_SE6a
ADC1_SE7a
VDD
VSS
USB0_DP
USB0_DM
VOUT33
VREGIN
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
VDDA
VREFH
VREFL
VSSA
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
XTAL32
EXTAL32
ALT1
PTE0
PTE1/
LLWU_P0
PTE2/
LLWU_P1
PTE3
PTE4/
LLWU_P2
PTE5
ALT2
ALT3
ALT4
SPI1_PCS1
SPI1_SOUT
UART1_TX
UART1_RX
SDHC0_D1
SDHC0_D0
SPI1_SCK UART1_CTS_b SDHC0_DCLK
SPI1_SIN
SPI1_PCS0
UART1_RTS_b SDHC0_CMD
UART3_TX SDHC0_D3
SPI1_PCS2 UART3_RX SDHC0_D2
ALT5
ALT6
ALT7
EzPort
I2C1_SDA
I2C1_SCL
RTC_CLKOUT
SPI1_SIN
SPI1_SOUT
K20 Sub-Family Data Sheet, Rev. 1, 6/2012.
66
Preliminary
Freescale Semiconductor, Inc.
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