K20P81M100SF2V2 Datasheet, PDF (41/71 Pages) Freescale Semiconductor, Inc – K20 Sub-Family

Peripheral operating requirements and behaviors
Figure 14. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
6.6.1.3 16-bit ADC with PGA operating conditions
Table 29. 16-bit ADC with PGA operating conditions
Symbol
V_DDA
V_REFPGA
Description
Supply voltage
PGA ref voltage
Conditions
Absolute
V_ADIN
V_CM
R_PGAD
R_AS
T_S
Input voltage
Input Common
Mode range
Differential input
impedance
Analog source
resistance
ADC sampling
time
Gain = 1, 2, 4, 8
Gain = 16, 32
Gain = 64
Min.
Typ.¹
Max.
1.71
—
3.6
VREF_OU VREF_OU VREF_OU
T
T
T
V_SSA
—
V_DDA
V_SSA
—
V_DDA
—
128
—
—
64
—
—
32
—
—
100
—
1.25
—
—
Unit
V
V
V
V
kΩ
Ω
µs
Table continues on the next page...
Notes
2, 3
IN+ to IN-⁴
5
6
K20 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
Preliminary
41
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