MSC8103_08 Datasheet, PDF (65/104 Pages) Freescale Semiconductor, Inc – Network Digital Signal Processor

AC Timings
DLLIN
22
PIO/TIMER/DMA inputs
PIO/TIMER/DMA outputs
23
42
Figure 2-23. PIO, Timer, and DMA Signal Diagram
Note:
The timing values refer to minimum system timing requirements. Actual implementation requires
conformance to the specific protocol requirements. Refer to Chapter 1 to identify the specific input and
output signals associated with the referenced internal controllers and supported communication protocols.
For example, FCC1 supports ATM/Utopia operation in slave mode, multi-PHY master direct polling
mode, and multi-PHY master multiplexed polling mode and each of these modes supports its own set of
signals; the direction (input or output) of some of the shared signal names depends on the selected mode.
2.6.8 JTAG Signals
Table 2-22. JTAG Timing
No.
Characteristics
500
TCK frequency of operation
501
TCK cycle time
502
TCK clock pulse width measured at 1.6 V
503
TCK rise and fall times
508
TMS, TDI data set-up time
509
TMS, TDI data hold time
510
TCK low to TDO data valid
511
TCK low to TDO high impedance
512
TRST assert time
513
TRST set-up time to TCK low
All frequencies
Min
0.0
25.0
12.5
0.0
6.0
3.0
0.0
0.0
100.0
40.0
Max
40.0
—
—
3.0
—
—
15.0
20.0
—
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCK
(Input)
V_IH
503
502
V_M
V_IL
501
502
V_M
503
Figure 2-24. Test Clock Input Timing Diagram
Freescale Semiconductor
MSC8103 Network Digital Signal Processor, Rev. 12
2-25