MSC8103_08 Datasheet, PDF (6/104 Pages) Freescale Semiconductor, Inc – Network Digital Signal Processor

Signals/Connections
For the signals
multiplexed on
Ports A–D,
see Figure 1-2
EOnCE Event
EED
EE0
EE1
EE[2–3]
EE[4–5]
BNK-
SEL[0–2]
TC[0–2]
32 ↔ A[0–31]
VDD → 14
5 ↔ TT[0–4]
VDDH → 25
VCCSYN → 1 ^P
VCCSYN1 → 1 ^O
W
E
GND → 37 _R
GNDSYN → 1
4 ↔ TSIZ[0–3]
1 ↔ TBST
1 ↔ IRQ1
3 → Reserved
1 ↔ BR
1 ↔ BG
GNDSYN1 → 1
1 ↔ ABB
1 ↔ TS
1 ↔ AACK
C
1 ← ARTRY
Port A
P
PA[31–6] ↔ 26 ^M
1 ↔ DBG
1 ↔ DBB
Port B
I
PB[31–18]
↔ 14
/
O
32 ↔ D[0–31]
16 ↔ D[32–47]
4 ↔ D[48–51]
Port C
P
1 ↔ D52
PC[31–22, 15–12, 7–4] ↔ 18 _{O 6}
R 0 ^{1 ↔ D53}
Port D
T x 1 ↔ D54
PD[31–29, 19–16, 7] ↔ 8 S
B
U
S
1
1
↔ D55
↔ D56
TMS → 1
1 ↔ D57
TDI → 1 ^J
1 ↔ D58
TCK
TRST
→1
→1
T
A
G
1 ↔ D59
1 ↔ D60
TDO ← 1
4 ↔ D[61–63]
GBL
BADDR[29–31]
IRQ2
IRQ3
HDI16 Signals
HD[0–15]
HA[0–3]
HCS1
Single DS
Double DS
HRW
HRD/HRD
HDS/HDS
HWR/HWR
Single HR
Double HR
HREQ/HREQ
HTRQ/HTRQ
HACK/HACK
HRRQ/HRRQ
HDSP
HDDS
H8BIT
HCS2
Reserved
RESET
Configuration
↔1
DBREQ ↔ 1
HPE ↔ 1
↔2
BTM[0–1] ↔ 2
PORESET → 1
RSTCONF → 1
HRESET ↔ 1
SRESET ↔ 1
1 ← Reserved
1 ↔ IRQ1
1 ↔ IRQ2
1 ↔ IRQ3
1 ↔ IRQ4
1 ↔ IRQ5
1 ↔ IRQ6
1 ↔ IRQ7
1 ↔ TA
1 ↔ TEA
1 ← NMI
1 → NMI_OUT
1 ↔ PSDVAL
1 ↔ IRQ7
DP0
DP1
DP2
DP3
DP4
DP5
DP6
DP7
INT_OUT
Reserved
IRQ1
Reserved
Reserved
DREQ3
DREQ4
DACK3
DACK4
CLKIN
MODCK[1–3]
CLKOUT
DLLIN
→1
→3
←1
→1
TEST → 1
THERM[1–2] ↔ 2
SPARE1, SPARE5 ↔ 2
8 → CS[0–7]
1 → BCTL1
2 → BADDR[27–28]
1 → ALE
M
E
1
→ BCTL0
M ^{8 → PWE[0–7]}
C 1 → PSDA10
1 → PSDWE
1 → POE
1 → PSDCAS
1 ↔ PGTA
1 → PSDAMUX
PSDDQM[0–7]
PUPMWAIT
PSDRAS
PPBS
IRQ[2–3, 5]
EXT_Br2
EXT_BG2
EXT_DBG2
EXT_BR3
EXT_BG3
EXT_DBG3
IRQ6
IRQ7
PBS[0–7]
PGPL0
PGPL1
PGPL2
PGPL3
PGPL4
PGPL5
Note:
Refer to the System Interface Unit (SIU) chapter in the MSC8103 Reference Manual for details on how to configure these pins.
Figure 1-1. MSC8103 External Signals
MSC8103 Network Digital Signal Processor, Rev. 12
1-2
Freescale Semiconductor