MSC8103_08 Datasheet, PDF (39/104 Pages) Freescale Semiconductor, Inc – Network Digital Signal Processor

CPM Ports
Table 1-10. Port D Signals (Continued)
Name
General-
Purpose I/O
Peripheral Controller:
Dedicated I/O
Protocol
PD17
BRG2O
Dedicated
I/O Data
Direction
Description
Output
Baud Rate Generator 2 Output
The CPM supports up to 8 BRGs for use internally to the MSC8103
and/or to provide an output to one of the 8 BRG pins.
FCC1: RXPRTY
UTOPIA
Input
FCC1: UTOPIA Receive Parity
This is the odd parity bit for RXD[0–7].
SPI: SPIMOSI
PD16
FCC1: TXPRTY
UTOPIA
Input/ Output
SPI: Master Output Slave Input
The SPI interface comprises our signals: master out slave in (SPIMOSI),
master in slave out (SPIMISO), clock (SPICLK) and select (SPISEL).
The SPI can be configured as a slave or master in single- or multiple-
master environments. When the SPI is a slave, SPICLK is the clock
input that shifts received data in from SPIMOSI and transmitted data out
through SPIMISO.
Output
FCC1: UTOPIA Transmit Parity
This is the odd parity bit for TXD[0–7].
SPI: SPIMISO
PD7
SMC1: SMSYN
Input/ Output
SPI: Master Input Slave Output
The SPI interface comprises four signals: master out slave in
(SPIMOSI), master in slave out (SPIMISO), clock (SPICLK), and select
(SPISEL). The SPI can be configured as a slave or master in single- or
multiple-master environments. When the SPI is a slave, SPICLK is the
clock input that shifts received data in from SPIMOSI and transmitted
data out through SPIMISO.
Input
SMC1: Serial Management Synchronization
The SMC interface consists of SMTXD, SMRXD, SMSYN and a clock.
Not all signals are used for all applications. SMCs are full-duplex ports
that support three protocols or modes: UART, transparent or general-
circuit interface (GCI).
FCC1: TXADDR3
UTOPIA master
Output
FCC1: UTOPIA Master Transmit Address Bit 3
This is master transmit address bit 3.
FCC1: TXADDR3
UTOPIA slave
Input
FCC1: UTOPIA Slave Transmit Address Bit 3
This is slave transmit address bit 3.
FCC1: TXCLAV2
UTOPIA multi-PHY master, direct
polling
Input
FCC1: UTOPIA Multi-PHY Master Transmit Cell Available 2 Direct
Polling
Asserted by an external UTOPIA slave PHY to indicate that it can accept
one complete ATM cell.
Freescale Semiconductor
MSC8103 Network Digital Signal Processor, Rev. 12
1-35