K40P144M100SF2 Datasheet, PDF (65/68 Pages) Freescale Semiconductor, Inc – K40 Sub-Family Data Sheet

144 144 Default
QFP BGA
120 B7 LCD_P31/
ADC1_SE7b
121 A7 LCD_P32
122 D6 LCD_P33
123 C6 LCD_P34
124 B6 LCD_P35
125 A6 LCD_P36
126 D5 LCD_P37
127 C5 LCD_P38
128 B5 LCD_P39
129 A5 LCD_P40
130 D4 LCD_P41/
ADC0_SE5b
131 C4 LCD_P42
132 B4 LCD_P43
133 A4 LCD_P44
134 A3 LCD_P45/
ADC0_SE6b
135 A2 LCD_P46/
ADC0_SE7b
136 M10 VSS
137 F8 VDD
138 A1 LCD_P47
139 B3 DISABLED
140 B2 DISABLED
141 B1 DISABLED
142 C3 DISABLED
143 C2 DISABLED
144 C1 DISABLED
ALT0
LCD_P31/
ADC1_SE7b
LCD_P32
LCD_P33
LCD_P34
LCD_P35
LCD_P36
LCD_P37
LCD_P38
LCD_P39
LCD_P40
LCD_P41/
ADC0_SE5b
LCD_P42
LCD_P43
LCD_P44
LCD_P45/
ADC0_SE6b
LCD_P46/
ADC0_SE7b
VSS
VDD
LCD_P47
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
PTC11
I2C1_SDA
I2S0_RXD
LCD_P31
PTC12
UART4_RTS
_b
LCD_P32
PTC13
UART4_CTS
_b
LCD_P33
PTC14
UART4_RX
LCD_P34
PTC15
UART4_TX
LCD_P35
PTC16
PTC17
PTC18
y _PTC19
r _PTD0
a _PTD1
in ^PTD2
PTD3
PTD4
PTD5
lim ^PTD6
CAN1_RX
CAN1_TX
SPI0_PCS0
SPI0_SCK
SPI0_SOUT
SPI0_SIN
SPI0_PCS1
SPI0_PCS2
SPI0_PCS3
UART3_RX
UART3_TX
UART3_RTS
_b
UART3_CTS
_b
UART2_RTS
_b
UART2_CTS
_b
UART2_RX
UART2_TX
UART0_RTS
_b
UART0_CTS
_b
UART0_RX
FTM0_CH4
FTM0_CH5
FTM0_CH6
LCD_P36
LCD_P37
LCD_P38
LCD_P39
LCD_P40
LCD_P41
EWM_IN
LCD_P42
LCD_P43
LCD_P44
EWM_OUT_b LCD_P45
FTM0_FLT0 LCD_P46
e _PTD7
r_PTD10
P^PTD11
CMT_IRO
SPI2_PCS0
UART0_TX
UART5_RTS
_b
UART5_CTS
FTM0_CH7
FB_AD9
SDHC0_CLKI FB_AD8
FTM0_FLT1 LCD_P47
_b
N
PTD12
SPI2_SCK
SDHC0_D4 FB_AD7
PTD13
SPI2_SOUT
SDHC0_D5 FB_AD6
PTD14
SPI2_SIN
SDHC0_D6 FB_AD5
PTD15
SPI2_PCS1
SDHC0_D7 FB_RW_b
Pinout
EzPort
8.2 K40 Pinouts
The below figure shows the pinout diagram for the devices supported by this document.
Many signals may be multiplexed onto a single pin. To determine what signals can be
used on which pin, see the previous section.
K40 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
65