K51P121M100SF2 Datasheet, PDF (64/70 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz

Pinout
8 Pinout
8.1 K51 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
121 Pin Name Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
MAP
BGA
• PTE0
ADC1_SE4a ADC1_SE4a PTE0
SPI1_PCS1 UART1_TX SDHC0_D1 FB_AD27 I2C1_SDA
• PTE1
ADC1_SE5a ADC1_SE5a PTE1
SPI1_SOUT UART1_RX SDHC0_D0 FB_AD26 I2C1_SCL
• PTE2
ADC1_SE6a ADC1_SE6a PTE2
SPI1_SCK UART1_CTS SDHC0_DCL FB_AD25
_b
K
• PTE3
ADC1_SE7a ADC1_SE7a PTE3
SPI1_SIN UART1_RTS SDHC0_CM FB_AD24
_b
D
• PTE4
DISABLED
PTE4
SPI1_PCS0 UART3_TX SDHC0_D3 FB_CS3_b/ FB_TA_b
FB_BE7_0_
BLS31_24_b
• PTE5
DISABLED
PTE5
SPI1_PCS2 UART3_RX SDHC0_D2 FB_TBST_b/
FB_CS2_b/
FB_BE15_8_
BLS23_16_b
• PTE6
DISABLED
PTE6
SPI1_PCS3 UART3_CTS I2S0_MCLK FB_ALE/ I2S0_CLKIN
_b
FB_CS1_b/
FB_TS_b
• VDD
VDD
VDD
• VSS
VSS
VSS
• USB0_DP USB0_DP USB0_DP
• USB0_DM USB0_DM USB0_DM
• VOUT33 VOUT33 VOUT33
• VREGIN VREGIN VREGIN
• ADC0_DP1/ ADC0_DP1/ ADC0_DP1/
OP0_DP0 OP0_DP0 OP0_DP0
• ADC0_DM1/ ADC0_DM1/ ADC0_DM1/
OP0_DM0 OP0_DM0 OP0_DM0
• ADC1_DP1/ ADC1_DP1/ ADC1_DP1/
OP1_DP0/ OP1_DP0/ OP1_DP0/
OP1_DM1 OP1_DM1 OP1_DM1
• ADC1_DM1/ ADC1_DM1/ ADC1_DM1/
OP1_DM0 OP1_DM0 OP1_DM0
• PGA0_DP/ PGA0_DP/ PGA0_DP/
ADC0_DP0/ ADC0_DP0/ ADC0_DP0/
ADC1_DP3 ADC1_DP3 ADC1_DP3
EzPort
K51 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
64
Preliminary
Freescale Semiconductor, Inc.