IMX53CEC Datasheet, PDF (64/204 Pages) Freescale Semiconductor, Inc – Applications Processors for Consumer Products

Electrical Characteristics
Table 40. EIM Asynchronous Timing Parameters Table Relative Chip Select
Ref
No.
Parameter
Determination by
Synchronous measured
Min
parameters ¹²
Max
(If 133 Mhz is
supported by
Unit
SOC)
MAXC
Output max. delay from
10
O
internal driving ADDR/control
FFs to chip outputs.
—
—
ns
MAXC Output max. delay from CSx
10
SO
internal driving FFs to CSx
out.
—
—
MAXDI DATA MAXIMUM delay from
5
chip input data to its internal
FF
WE43
Input Data Valid to CSx_B MAXCO - MAXCSO + MAXDI
Invalid
—
MAXCO ^-
MAXCSO +
MAXDI
—
—
ns
WE44 CSx_B Invalid to Input Data
0
invalid
0
—
ns
WE45 CSx_B Valid to BEy_B Valid WE12 - WE6 + (WBEA - CSA)
—
3 + (WBEA - CSA) ns
(Write access)
WE46
BEy_B Invalid to CSx_B
Invalid (Write access)
WE7 - WE13 + (WBEN -
CSN)
—
-3 + (WBEN - CSN) ns
MAXD
TI
DTACK MAXIMUM delay from
chip dtack input to its internal
FF + 2 cycles for
synchronization
—
—
—
WE47 Dtack Active to CSx_B Invalid
MAXCO - MAXCSO +
MAXDTI
MAXCO -
MAXCSO +
MAXDTI
—
ns
WE48
CSx_B Invalid to Dtack
0
invalid
0
—
ns
1 _{Parameters WE4... WE21 value see column BCD = 0 in Table 39}
2 _{All config. parameters (CSA,CSN,WBEA,WBEN,ADVA,ADVN,OEN,OEA,RBEA & RBEN) are in cycle units.}
3 _{CS Assertion. This bit field determines when CS signal is asserted during read/write cycles.}
4 _{CS Negation. This bit field determines when CS signal is negated during read/write cycles.}
5 _{t is axi_clk cycle time.}
6 _{BE Assertion. This bit field determines when BE signal is asserted during read cycles.}
7 _{BE Negation. This bit field determines when BE signal is negated during read cycles.}
i.MX53xD Applications Processors for Consumer Products, Rev. 2
64
Freescale Semiconductor