MKW01Z128 Datasheet, PDF (63/67 Pages) Freescale Semiconductor, Inc – Highly-integrated, cost-effective single-package solution for sub-1 GHz applications

Peripheral operating requirements and behaviors
Table 27. I ²C timing (continued)
Characteristic
Symbol
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START
condition
Data hold time for I²C bus devices
Data set-up time
Rise time of SDA and SCL signals
Fall time of SDA and SCL signals
Set-up time for STOP condition
Bus free time between STOP and
START condition
Pulse width of spikes that must be
suppressed by the input filter
t_HD; STA
t_LOW
t_HIGH
t_SU; STA
t_HD; DAT
t_SU; DAT
t_r
t_f
t_SU; STO
t_BUF
t_SP
Standard Mode
Fast Mode
Unit
Minimum Maximum Minimum Maximum
4
—
0.6
—
µs
4.7
4
4.7
0¹
250⁴
—
—
4
4.7
N/A
—
1.3
—
µs
—
0.6
—
µs
—
0.6
—
µs
3.45²
0³
0.9¹
µs
—
100², ⁵
—
 ns
1000
20 +0.1C_b6
300
ns
300
20 +0.1C_b5
300
 _ns
—
0.6
—
µs
—
1.3
—
µs
N/A
0
50
ns
1. The master mode I²C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.
2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
3. Input signal Slew = 10 ns and Output Load = 50 pF
4. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
5. A Fast mode I²C bus device can be used in a Standard mode I2C bus system, but the requirement t_{SU; DAT} ≥ 250 ns must
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line t_rmax + t_{SU; DAT}
= 1000 + 250 = 1250 ns (according to the Standard mode I²C bus specification) before the SCL line is released.
6. C_b = total capacitance of the one bus line in pF.
SDA
t_f
SCL
t_LOW
t_r
t_{SU; DAT}
t_f
t_{HD; STA}
t_SP
t_r
t_BUF
S
t_{HD; STA}
t_{HD; DAT}
t_HIGH
t_{SU; STA}
SR
t_{SU; STO}
P
S
Figure 16. Timing definition for fast and standard mode devices on the I²C bus
2.8.3 UART
See General switching specifications.
MKW01 MCU Section Data Sheet Data Sheet, Rev. 5, 3/2014.
36
Freescale Semiconductor, Inc.