IMX6DQAEC Datasheet, PDF (62/165 Pages) Freescale Semiconductor, Inc – i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors

Electrical Characteristics
Table 44. DDR3/DDR3L Write Cycle (continued)
ID
Parameter
DDR22 DRAM_SDQSx_P high level width
DDR23 DRAM_SDQSx_P low level width
CK = 532 MHz
Symbol
Unit
Min Max
tDQSH 0.45 0.55 tCK
tDQSL 0.45 0.55 tCK
1 _{To receive the reported setup and hold values, write calibration should be performed in order to locate the DRAM_SDQSx_P}
in the middle of DRAM_DATAxx window.
2 _{All measurements are in reference to Vref level.}
3 _{Measurements were taken using balanced load and 25  resistor from outputs to DRAM_VREF.}
Figure 26 shows the DDR3/DDR3L read timing diagram. The timing parameters for this diagram appear
in Table 45.
DRAM_SDCLKx_P
DRAM_SDCLKx_N
DRAM_SDQSx_P(input)
DRAM_DATAxx (input)
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DDR26
Figure 26. DDR3/DDR3L Read Cycle
Table 45. DDR3/DDR3L Read Cycle
CK = 532 MHz
ID
Parameter
Symbol
Unit
Min
Max
DDR26 Minimum required DRAM_DATAxx valid window width
—
450
—
ps
1 _{To receive the reported setup and hold values, read calibration should be performed in order to locate the DRAM_SDQSx_P}
in the middle of DRAM_DATAxx window.
2 _{All measurements are in reference to Vref level.}
3 _{Measurements were done using balanced load and 25  resistor from outputs to DRAM_VREF.}
i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2.3
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Freescale Semiconductor