IMX6DQAEC Datasheet, PDF (132/165 Pages) Freescale Semiconductor, Inc – i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors

Electrical Characteristics
Table 89. SSI Transmitter Timing with External Clock (continued)
ID
Parameter
Min
Max
Unit
SS44
SS45
SS46
Synchronous External Clock Operation
AUDx_RXD setup before AUDx_TXC falling
10.0
AUDx_RXD hold after AUDx_TXC falling
2.0
AUDx_RXD rise/fall time
—
—
ns
—
ns
6.0
ns
NOTE
• All the timings for the SSI are given for a non-inverted serial clock
polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have
been inverted, all the timing remains valid by inverting the clock signal
AUDx_TXC/AUDx_RXC and/or the frame sync
AUDx_TXFS/AUDx_RXFS shown in the tables and in the figures.
• All timings are on Audiomux Pads when SSI is being used for data
transfer.
• AUDx_TXC and AUDx_RXC refer to the Transmit and Receive
sections of the SSI.
• The terms WL and BL refer to Word Length (WL) and Bit Length (BL).
• For internal Frame Sync operation using external clock, the frame sync
timing is same as that of transmit data (for example, during AC97 mode
of operation).
4.11.20.4 SSI Receiver Timing with External Clock
Figure 99 depicts the SSI receiver external clock timing and Table 90 lists the timing parameters for the
receiver timing with the external clock.
SS23
AUDx_TXC
(Input)
AUDx_TXFS (bl)
(Input)
SS28
AUDx_TXFS (wl)
(Input)
AUDx_RXD
(Input)
SS22
SS26
SS25
SS30
SS32
SS35
SS40
SS24
SS41
SS36
Figure 99. SSI Receiver External Clock Timing Diagram
SS34
i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2.3
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Freescale Semiconductor