DSP56301 Datasheet, PDF (62/124 Pages) Freescale Semiconductor, Inc – 24-Bit Digital Signal Processor

Specifications
Table 2-19. Universal Bus Mode, Synchronous Port A Type Host Timing (Continued)
No.
Characteristic
Expression
80 MHz
Min Max
100 MHz
Unit
Min Max
330 HIRQ High Impedance from Data Strobe Assertion
(HIRH = 1, HIRD = 0)^1,6
331 HIRQ Active from Data Strobe Deassertion
(HIRH = 1, HIRD = 0)¹
332 HIRQ Deasserted Hold from Data Strobe Deassertion¹
346 HRST Assertion to Host Port Pins High Impedance²
80 MHz: 2.5 × T_C + 24.7 — 55.9
ns
100 MHz: 2.5 × T_C + 21.5
— 46.5 ns
2.5 × T_C
31.3 — 25.0 — ns
2.5 × T_C
31.3 — 25.0 — ns
— 22.2 — 19.6 ns
347 HBS Assertion to CLKOUT Rising Edge
348 Data Strobe Deassertion to CLKOUT Rising Edge¹
4.3
—
3.4
— ns
7.4
—
5.9
— ns
Notes: 1. The Data Strobe is HRD or HWR in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.
2. HTA, HDRQ, and HRST may be programmed as active-high or active-low. In the example timing diagrams, HDRQ and HRST
are shown as active-high and HTA is shown as active low.
3. The Read Data Strobe is HRD in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.
4. The Write Data Strobe is HWR in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.
5. HTA requires an external pull-down resistor if programmed as active high (HTAP = 0); or an external pull-up resistor if
programmed as active low (HTAP = 1). The resistor value should be consistent with the DC specifications.
6. HIRQ requires an external pull-up resistor if programmed as open drain (HIRD = 0). The resistor value should be consistent
with the DC specifications.
7. “LT” is the value of the latency timer register (CLAT) as programmed by the user during self configuration.
8. Values are valid for V_CC = 3.3 ± 0.3V
HA[10–0]
HDS
HRD
HWR
HBS
HIRQ
(HIRD = 1,
HIRH = 1)
HIRQ
(HIRD = 0,
HIRH = 1)
301
305
307
308
310
309
329
328
330
302
332
331
Figure 2-27. Universal Bus Mode I/O Access Timing
2-36
DSP56301 Technical Data, Rev. 10
Freescale Semiconductor