DSP56301 Datasheet, PDF (1/124 Pages) Freescale Semiconductor, Inc – 24-Bit Digital Signal Processor

Freescale Semiconductor
Technical Data
DSP56301
Rev. 10, 7/2006
DSP56301
24-Bit Digital Signal Processor
52
66
Triple
Timer
Host
Interface
ESSI
3
Memory Expansion Area
SCI
Program
X Data
RAM
4096 × 24 bits
(Default)
RAM
2048 × 24
bits
(Default)
Y Data
RAM
2048 × 24
bits
(Default)
Address
Generator
Unit
Six-Channel
DMA Unit
Boot-
strap
ROM
Internal
Data
Bus
Switch
EXTAL
XTAL
Clock
PLL
2
RESET
PINIT/NMI
Program
Interrupt
Controller
Peripheral
Expansion Area
24-Bit
DSP56300
Core
YAB
XAB
PAB
DAB
DDB
YDB
XDB
PDB
GDB
24
External
Address
Bus
Switch
External ¹⁴
Bus
Interface
and
I-Cache
Control
24
External
Data
Bus
Program
Decode
Controller
Power
Management
Program
Address
Generator
Data ALU
24 × 24+56^→56-bit MAC
Two 56-bit Accumulators
56-bit Barrel Shifter
JTAG
OnCE™
6
MODD/IRQD
MODC/IRQC
MODB/IRQB
MODA/IRQA
Figure 1. DSP56301 Block Diagram
The DSP56301 is intended
for general-purpose digital
signal processing,
particularly in multimedia
and telecommunication
applications, such as video
conferencing and cellular
telephony.
What’s New?
Rev. 10 includes the following
changes:
• Removes all references to
Motorola. No specifications or
part numbers were changed.
The DSP56301 is a member of the DSP56300 core family of programmable CMOS Digital Signal Processors
(DSPs). This family uses a high-performance, single clock cycle per instruction engine. Significant architectural
features of the DSP56300 core family include a barrel shifter, 24-bit addressing, instruction cache, and DMA. The
DSP56301 offers 80/100 MIPS using an internal 80/100 MHz clock at 3.0–3.6 volts. The DSP56300 core family
offers a rich instruction set and low power dissipation, as well as increasing levels of speed and power, enabling
wireless, telecommunications, and multimedia products.
© Freescale Semiconductor, Inc., 1996, 2006. All rights reserved.