DSP56301 Datasheet, PDF (56/124 Pages) Freescale Semiconductor, Inc – 24-Bit Digital Signal Processor

Specifications
2.5.5.4 Arbitration Timings
Table 2-16. Arbitration Bus Timings¹.
No.
Characteristics
Expression²
80 MHz
100 MHz
Unit
Min Max Min Max
212 CLKOUT high to BR assertion/deassertion³
1.0
4.5
0.0
4.0
ns
213 BG asserted/deasserted to CLKOUT high
(setup)
5.0
—
4.0
—
ns
214 CLKOUT high to BG deasserted/asserted
(hold)
0.0
—
0.0
—
ns
215 BB deassertion to CLKOUT high (input setup)
5.0
—
4.0
—
ns
216 CLKOUT high to BB assertion (input hold)
0.0
—
0.0
—
ns
217 CLKOUT high to BB assertion (output)
1.0
4.5
0.0
4.0
ns
218 CLKOUT high to BB deassertion (output)
1.0
4.5
0.0
4.0
ns
219 BB high to BB high impedance (output)
—
5.6
—
4.5
ns
220 CLKOUT high to address and controls active
221 CLKOUT high to address and controls high
impedance
0.25 × T_C
0.75 × T_C
3.1
—
2.5
—
ns
—
9.4
—
7.5
ns
222 CLKOUT high to AA active
0.25 × T_C
3.1
—
2.5
—
ns
223 CLKOUT high to AA deassertion
maximum: 0.25 × T_C + 4.0
4.1
7.1
2.0
6.5
ns
224 CLKOUT high to AA high impedance
0.75 × T_C
—
9.4
—
7.5
ns
Notes: 1. Synchronous Bus Arbitration is not recommended. Use Asynchronous mode whenever possible.
2. An expression is used to compute the maximum or minimum value listed, as appropriate. For timing 223, the minimum is an
absolute value.
3. T212 is valid for Address Trace mode when the ATE bit in the Operating Mode Register is set. BR is deasserted for internal
accesses and asserted for external accesses.
2-30
DSP56301 Technical Data, Rev. 10
Freescale Semiconductor