56F8335_07 Datasheet, PDF (62/160 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controller

Table 4-30 GPIOB Registers Address Map
(GPIOB_BASE = $00 F300)
Register Acronym Address Offset
Register Description
GPIOB_PUR
GPIOB_DR
GPIOB_DDR
GPIOB_PER
GPIOB_IAR
GPIOB_IENR
GPIOB_IPOLR
GPIOB_IPR
GPIOB_IESR
GPIOB_PPMODE
GPIOB_RAWDATA
$0
Pull-up Enable Register
$1
Data Register
$2
Data Direction Register
$3
Peripheral Enable Register
$4
Interrupt Assert Register
$5
Interrupt Enable Register
$6
Interrupt Polarity Register
$7
Interrupt Pending Register
$8
Interrupt Edge-Sensitive Register
$9
Push-Pull Mode Register
$A
Raw Data Input Register
Reset Value
0 x 00FF
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 00FF
—
Table 4-31 GPIOC Registers Address Map
(GPIOC_BASE = $00 F310)
Register Acronym Address Offset
Register Description
GPIOC_PUR
GPIOC_DR
GPIOC_DDR
GPIOC_PER
GPIOC_IAR
GPIOC_IENR
GPIOC_IPOLR
GPIOC_IPR
GPIOC_IESR
GPIOC_PPMODE
GPIOC_RAWDATA
$0
Pull-up Enable Register
$1
Data Register
$2
Data Direction Register
$3
Peripheral Enable Register
$4
Interrupt Assert Register
$5
Interrupt Enable Register
$6
Interrupt Polarity Register
$7
Interrupt Pending Register
$8
Interrupt Edge-Sensitive Register
$9
Push-Pull Mode Register
$A
Raw Data Input Register
Reset Value
0 x 07FF
0 x 0000
0 x 0000
0 x 07FF
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 07FF
—
56F8335 Technical Data, Rev. 5
62
Freescale Semiconductor
Preliminary