56F8335_07 Datasheet, PDF (18/160 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controller

Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued)
Signal
Name
Pin No.
Type
State
During
Reset
Signal Description
V_{SSA_ADC}
95
OCR_DIS
71
Supply
Input
Input
ADC Analog Ground — This pin supplies an analog ground to
the ADC modules.
On-Chip Regulator Disable —
Tie this pin to V_SS to enable the on-chip regulator
Tie this pin to V_DD to disable the on-chip regulator
V_CAP1
49
V_CAP2
122
V_CAP3
75
V_CAP4
13
V_PP1
119
V_PP2
5
CLKMODE
79
Supply
Input
Input
Supply
Input
This pin is intended to be a static DC signal from power-up
to shut down. Do not try to toggle this pin for power savings
during operation.
V_CAP1 - 4 — When OCR_DIS is tied to V_SS (regulator enabled),
connect each pin to a 2.2μF or greater bypass capacitor in order
to bypass the core logic voltage regulator, required for proper
chip operation. When OCR_DIS is tied to V_DD (regulator
disabled), these pins become V_{DD_CORE} and should be
connected to a regulated 2.5V power supply.
Note: This bypass is required even if the chip is powered
with an external supply.
V_PP1 - 2 — These pins should be left unconnected as an open
circuit for normal functionality.
Input
Clock Input Mode Selection — This input determines the
function of the XTAL and EXTAL pins.
1 = External clock input on XTAL is used to directly drive the
input clock of the chip. The EXTAL pin should be grounded.
0 = A crystal or ceramic resonator should be connected between
XTAL and EXTAL.
EXTAL
74
Input
Input
External Crystal Oscillator Input — This input can be
connected to an 8MHz external crystal. Tie this pin low if XTAL is
driven by an external clock source.
XTAL
73
Input/
Chip-driven Crystal Oscillator Output — This output connects the internal
Output
crystal oscillator output to an external crystal.
If an external clock is used, XTAL must be used as the input and
EXTAL connected to GND.
The input clock can be selected to provide the clock directly to
the core. This input clock can also be selected as the input clock
for the on-chip PLL.
56F8335 Technical Data, Rev. 5
18
Freescale Semiconductor
Preliminary