MC68C812A4 Datasheet, PDF (6/18 Pages) Freescale Semiconductor, Inc – Technical Supplement MC68C812A4 3.3V Electrical Characteristics

Freescale Semiconductor, Inc.
Table 7 Analog Converter Characteristics (Operating)
V_DD = 3.3 Vdc ± 0.3V, V_SS = 0 Vdc, T_A = T_L to T_H, ATD Clock = 2 MHz, unless otherwise noted
Characteristic
Symbol
Min Typical Max Unit
8-bit resolution¹
2 counts
24
mV
Differential non-linearity²
DNL
−0.5
+0.5 count
Integral non-linearity²
INL
−1
+1
count
Absolute error^2,3 2, 4, 8, and 16 ATD sample clocks
AE
−2
+2
count
Maximum source impedance
R_S
20
See note⁴ KΩ
NOTES:
1. V_RH − V_RL ≥ 3.072V
2. At V_REF = 3.072V, one 8-bit count = 12 mV.
3. Eight-bit absolute error of 2 counts (24 mV) includes 1/2 count (6 mV) inherent quantization error and 1 1/2
counts (18 mV) circuit (differential, integral, and offset) error.
4. Maximum source impedance is application-dependent. Error resulting from pin leakage depends on junction
leakage into the pin and on leakage due to charge-sharing with internal capacitance.
Error from junction leakage is a function of external source impedance and input leakage current. Expected error
in result value due to junction leakage is expressed in voltage (V_ERRJ):
V_ERRJ = R_S × I_OFF
where I_OFF is a function of operating temperature. Charge-sharing effects with internal capacitors are a function of
ATD clock speed, the number of channels being scanned, and source impedance. For 8-bit conversions, charge
pump leakage is computed as follows:
V_ERRJ = .25pF × V_DDA × R_S × ATDCLK/(8 × number of channels)
Table 8 ATD AC Characteristics (Operating)
V_DD = 3.3 Vdc ± 0.3V, V_SS = 0 Vdc, T_A = T_L to T_H, ATD Clock = 2 MHz, unless
otherwise noted
Characteristic
ATD operating clock frequency
Conversion time per channel
0.5 MHz ≤ f_ATDCLK ≤ 2 MHz
18 ATD clocks
32 ATD clocks
Stop recovery time V_DDA = 3.3V
Symbol
f_ATDCLK
t_CONV
t_SR
Min
0.5
9.0
16.0
Max Unit
2.0 MHz
32.0
µs
60.0
µs
50
µs
6
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