MC68C812A4 Datasheet, PDF (14/18 Pages) Freescale Semiconductor, Inc – Technical Supplement MC68C812A4 3.3V Electrical Characteristics

Freescale Semiconductor, Inc.
Table 12 Non-Multiplexed Expansion Bus Timing
V_DD = 3.3 Vdc ± 0.3V, V_SS = 0 Vdc, T_A = T_L to T_H, unless otherwise noted
Num
Characteristic¹
Delay Symbol 5 MHz Unit
Min Max
Frequency of operation (E-clock frequency)
f_o
dc 5.0
1 Cycle time
t_cyc = 1/f_o
t_cyc
200 —
2 Pulse width, E low
3 Pulse width, E high²
PW_EL = t_cyc/2 + delay −2 PW_EL 98 —
PW_EH = t_cyc/2 + delay −2 PW_EH 98 —
5 Address delay time
t_AD = t_cyc/4 + delay 29
t_AD
— 79
6 Address hold time
—
t_AH
20 —
7 Address valid time to E rise t_AV = PW_EL − t_AD —
t_AV
28 —
11 Read data setup time
—
t_DSR
30 —
12 Read data hold time
—
t_DHR
0—
13 Write data delay time
t_DDW = t_cyc/4 + delay
25
t_DDW
— 75
14 Write data hold time
—
15 Write data setup time²
t_DSW = PW_EH − t_DDW
—
t_DHW
t_DSW
20 —
23 —
16 Read/write delay time
t_RWD = t_cyc/4 + delay 20
t_RWD
— 70
17
Read/write valid time to E rise
t_RWV = PW_EL − t_RWD
—
t_RWV
28 —
18 Read/write hold time
—
t_RWH
20 —
19 Low strobe delay time
t_LSD = t_cyc/4 + delay 20
t_LSD
— 70
20
Low strobe valid time to E rise
t_LSV = PW_EL − t_LSD
—
t_LSV
28 —
21 Low strobe hold time
—
t_LSH
20 —
22 Address access time² t_ACCA = t_cyc − t_AD − t_DSR
—
t_ACCA
— 100
23 Access time from E rise² t_ACCE = PW_EH − t_DSR
—
t_ACCE
—
68
26 Chip select delay time
t_CSD = t_cyc/4 + delay 29
t_CSD
— 79
27
Chip select access time²
t_ACCS = t_cyc − t_CSD − t_DSR
—
t_ACCS
— 100
28 Chip select hold time
—
t_CSH
0 10
29 Chip select negated time t_CSN = t_cyc/4 + delay
5
t_CSN
55 —
NOTES:
1. All timings are calculated for normal port drives.
2. This characteristic is affected by clock stretch.
Add N × t_cyc where N = 0, 1, 2, or 3, depending on the number of clock stretches.
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
14
For More Information On This Product,
Go to: www.freescale.com