MC68C812A4 Datasheet, PDF (16/18 Pages) Freescale Semiconductor, Inc – Technical Supplement MC68C812A4 3.3V Electrical Characteristics

Freescale Semiconductor, Inc.
Table 13 SPI Timing
V_DD = 3.3 Vdc ± 0.3V, V_SS = 0 Vdc, T_A = T_L to T_H , 130 pF load on all SPI pins¹
Num
Function
Symbol
Min
Max
Unit
Operating Frequency
Master
Slave
f_op
DC
DC
1/2
1/2
E-clock
frequency
SCK Period
1 Master
Slave
Enable Lead Time
2 Master
Slave
Enable Lag Time
3 Master
Slave
Clock (SCK) High or Low Time
4 Master
Slave
Sequential Transfer Delay
5 Master
Slave
Data Setup Time (Inputs)
6 Master
Slave
t_sck
2
256
t_cyc
2
—
t_cyc
t_lead
1/2
1
—
t_sck
—
t_cyc
t_lag
1/2
—
t_sck
1
—
t_cyc
t_wsck
t_cyc − 60 128 t_cyc
ns
t_cyc − 30
—
ns
t_td
1/2
—
t_sck
1
—
t_cyc
t_su
30
—
ns
30
—
ns
Data Hold Time (Inputs)
7 Master
Slave
t_hi
0
—
ns
30
—
ns
8 Slave Access Time
9 Slave MISO Disable Time
Data Valid (after SCK Edge)
10 Master
Slave
t_a
—
t_dis
—
1
t_cyc
1
t_cyc
t_v
—
50
ns
—
50
ns
Data Hold Time (Outputs)
11 Master
Slave
t_ho
0
—
ns
0
—
ns
Rise Time
12 Input
Output
t_ri
—
t_cyc − 30
ns
t_ro
—
30
ns
Fall Time
13 Input
Output
t_fi
—
t_cyc − 30
ns
t_fo
—
30
ns
NOTES:
1. All AC timing is shown with respect to 20% V_DD and 70% V_DD levels unless otherwise noted.
16
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