MCF5282 Datasheet, PDF (570/766 Pages) Freescale Semiconductor, Inc – Microcontroller User’s Manual

Queued Analog-to-Digital Converter (QADC)
16
PQA4
PQA0
PQB3
PQB0
V_RH
V_RL
V_DDA
V_SSA
Chan. Decode & MUX
16:1
10-bit A/D Converter
Input
4
6
Bias Circuit
CHAN[5:0]
Analog
Power
Sample
Buffer
CSAMP
10
Internal Power-
Channel Down
Decode
2
State Machine & Logic
SAR Timing
STOP
RST
QCLK
IST
Start Conv
End OF Conv
10
10
SAR[9:0]
Compar-
ator
Successive
Approximation
Register
Figure 28-19. QADC Analog Subsystem Block Diagram
28.7.3.2 Conversion Cycle Times
Total conversion time is made up of initial sample time, final sample time, and resolution time. Initial
sample time refers to the time during which the selected input channel is coupled through the sample buffer
amplifier to the sample capacitor. The sample buffer is used to quickly reproduce its input signal on the
sample capacitor and minimize charge sharing errors. During the final sampling period the amplifier is
bypassed, and the multiplexer input charges the sample capacitor array directly for improved accuracy.
During the resolution period, the voltage in the sample capacitor is converted to a digital value and stored
in the SAR as shown in Figure 28-20.
Initial sample time is fixed at two QCLK cycles. Final sample time can be 2, 4, 8, or 16 QCLK cycles,
depending on the value of the IST field in the CCW. Resolution time is 10 QCLK cycles.
A conversion requires a minimum of 14 QCLK cycles (7 μs with a 2.0-MHz QCLK). If the maximum final
sample time period of 16 QCLKs is selected, the total conversion time is 28 QCLKs or 14 μs (with a
2.0-MHz QCLK).
28-32
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Freescale Semiconductor