MCF5282 Datasheet, PDF (540/766 Pages) Freescale Semiconductor, Inc – Microcontroller User’s Manual

Queued Analog-to-Digital Converter (QADC)
28.2 Block Diagram
External
MUX Address
External
Triggers
8 Analog Channels
(18 with External MUXing)
Analog Power
Inputs
Reference
Inputs
Analog Input MUX
and Digital
Signal Functions
Digital
Control
IPBUS
Interface
10-bit
Analog-to-Digital
Converter
64-Entry Queue
of 10-bit
Conversion
Command Words
(CCWs)
64-Entry Table
of 10-bit
Results
10-bit to 16-bit
Result Alignment
Figure 28-1. QADC Block Diagram
28.3 Modes of Operation
This subsection describes the two modes of operation in which the QADC does not perform conversions
in a regular fashion:
• Debug mode
• Stop mode
28.3.1 Debug Mode
The QDBG bit in the module configuration register (QADCMCR) governs behavior of the QADC when
the CPU enters background debug mode. When QDBG is clear, the QADC operates normally and is
unaffected by CPU background debug mode. See Section 28.6.1, “QADC Module Configuration Register
(QADCMCR).
When QDBG is set and the CPU enters background debug mode, the QADC finishes any conversion in
progress and then freezes. This is QADC debug mode. Depending on when debug mode is entered, the
three possible queue freeze scenarios are:
• When a queue is not executing, the QADC freezes immediately.
• When a queue is executing, the QADC completes the current conversion and then freezes.
28-2
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Freescale Semiconductor