MSC7119_08 Datasheet, PDF (55/60 Pages) Freescale Semiconductor, Inc – Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC

Hardware Design Considerations
Driver
V_DDQ
V_TT
RT
RS
Receiver
V_REF
V_SS
Figure 37. SSTL Power Value
3.5.1 V_REF and V_TT Design Constraints
V_TT and V_REF are isolated power supplies at the same voltage, with V_TT as a high current power source. This section outlines
the voltage supply design needs and goals:
• Minimize the noise on both rails.
• V_TT must track variation in the V_REF DC offsets. Although they are isolated supplies, one possible solution is to use a
single IC to generate both signals.
• Both references should have minimal drift over temperature and source supply.
• It is important to minimize the noise from coupling onto V_REF as follows:
— Isolate V_REF and shield it with a ground trace.
— Use 15–20 mm track.
— Use 20–30 mm clearance between other traces for isolating.
— Use the outer layer route when possible.
— Use distributed decoupling to localize transient currents and return path and decouple with an inductance less than
3 nH.
• Max source/sink transient currents of up to 1.8 A for a 32-bit data bus.
• Use a wide island trace on the outer layer:
— Place the island at the end of the bus.
— Decouple both ends of the bus.
— Use distributed decoupling across the island.
— Place SSTL termination resistors inside the V_TT island and ensure a good, solid connection.
• Place the V_TT regulator as closely as possible to the termination island.
— Reduce inductance and return path.
— Tie current sense pin at the midpoint of the island.
3.5.2 Decoupling
The DDR decoupling considerations are as follows:
• DDR memory requires significantly more burst current than previous SDRAMs.
• In the worst case, up to 64 drivers may be switching states.
• Pay special attention and decouple discrete ICs per manufacturer guidelines.
• Leverage V_TT island topology to minimize the number of capacitors required to supply the burst current needs of the
termination rail.
• See the Micron DesignLine publication entitled Decoupling Capacitor Calculation for a DDR Memory Channel
(http://download.micron.com/pdf/pubs/designline/3Q00dl1-4.pdf).
MSC7119 Data Sheet, Rev. 8
Freescale Semiconductor
55