MSC7119_08 Datasheet, PDF (4/60 Pages) Freescale Semiconductor, Inc – Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC

Pin Assignments
1 Pin Assignments
This section includes diagrams of the MSC7119 package ball grid array layouts and pinout allocation tables.
1.1 MAP-BGA Ball Layout Diagrams
Top and bottom views of the MAP-BGA package are shown in Figure 2 and Figure 3 with their ball location index numbers.
Top View
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
A
GND GND DQM1 DQS2 CK
CK HD15 HD12 HD10 HD7 HD6 HD4 HD1 HD0 GND BM3 NC
NC
NC
NC
B
V_DDM NC
CS0 DQM2 DQS3 DQS0 CKE
WE HD14 HD11 HD8 HD5 HD2
NC
BM2
NC
NC
NC
NC
NC
C
D24 D30 D25 CS1 DQM3 DQM0 DQS1 RAS CAS HD13 HD9 HD3 NC
NC
NC
NC
NC
NC
NC
NC
D
V_DDM D28
D27
GND VDDM VDDM VDDM VDDM VDDM VDDM VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDC
NC
NC
NC
E
GND
D26
D31 VDDM VDDM VDDC VDDC VDDC VDDC VDDM VDDIO VDDIO VDDIO VDDIO VDDIO VDDC VDDC
NC
NC
NC
F
V_DDM D15
D29 VDDC VDDC VDDC GND GND GND VDDM VDDM GND GND GND VDDIO VDDC VDDC
NC
NC
NC
G
GND D13 GND VDDM VDDM GND GND GND GND GND GND GND GND GND VDDIO VDDIO VDDC NC
NC
NC
H
D14
D12
D11 VDDM VDDM GND GND GND GND GND GND GND GND GND VDDIO VDDIO VDDC NC
HA2 HA1
J
D10 VDDM D9 VDDM VDDM VDDM GND GND GND GND GND GND GND GND GND VDDIO VDDC HA3 HACK HREQ
K
D0
GND
D8
V_DDC V_DDM GND GND GND GND GND GND GND GND GND V_DDIO V_DDIO V_DDC HA0 HDDS HDS
L
D1
GND
D3
V_DDC V_DDM GND GND GND GND GND GND GND GND V_DDIO V_DDIO V_DDIO V_DDC HCS2 HCS1 HRW
M
D2 VDDM D5 VDDM VDDM GND GND GND GND GND GND GND GND GND GND VDDC VDDC SDA UTXD URXD
N
D4
D6
V_REF V_DDM V_DDM V_DDM GND GND GND GND GND GND GND GND V_DDIO V_DDC V_DDC CLKIN SCL V_SSPLL
P
D7
D17
D16 VDDM VDDM VDDM GND GND GND GND GND GND GND GND VDDIO VDDIO VDDC PORESET TPSEL VDDPLL
R
GND
D19
D18 VDDM VDDM VDDM GND VDDM GND VDDM GND GND VDDIO GND VDDIO VDDIO VDDC TDO
EE0 TEST0
T
V_DDM D20
D22 VDDM VDDM VDDC VDDM VDDM VDDC VDDM VDDM VDDIO VDDIO VDDIO VDDIO VDDC VDDC MDIO TMS HRESET
U
GND
D21
D23 VDDM VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC COL TCK TRST
V
V_DDM NC
A13 A11 A10
A5
A2 BA0 NC EVNT0 EVNT4 T0TCK T1RFS T1TD TX_ER RXD2 RXD0 TX_EN CRS TDI
W
GND VDDM A12
A8
A7
A6
A3
NC EVNT1 EVNT2 T0RFS T0TFS T1RD T1TFS TXD2 RXD3 TXD1 TXCLK RX_ER MDC
Y
V_DDM GND
A9
A1
A0
A4 BA1 NMI EVNT3 T0RCK T0RD TOTD T1RCK T1TCK TXD3 RXCLK TXD0 RXD1 GND RX_DV
Figure 2. MSC7119 Molded Array Process-Ball Grid Array (MAP-BGA), Top View
MSC7119 Data Sheet, Rev. 8
4
Freescale Semiconductor