MSC7119_08 Datasheet, PDF (30/60 Pages) Freescale Semiconductor, Inc – Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC

Electrical Characteristics
2.5.6.2 Transmit Signal Timing
Table 22. Transmit Signal Timing
No.
Characteristics
800 Transmit clock period:
• MII: TXCLK
• RMII: REFCLK
801 Transmit clock pulse width high—as a percent of clock period
• MII: RXCLK
• RMII: REFCLK
802 Transmit clock pulse width low—as a percent of clock period:
• MII: RXCLK
• RMII: REFCLK
805 Transmit clock to TXDn, TX_EN, TX_ER invalid
806 Transmit clock to TXDn, TX_EN, TX_ER valid
800
801
802
Transmit
clock
TXDn
TX_EN
TX_ER
806
805
Valid
Figure 11. Ethernet Receive Signal Timing
2.5.6.3 Asynchronous Input Signal Timing
Table 23. Asynchronous Input Signal Timing
No.
Characteristics
807 • MII: CRS and COL minimum pulse width (1.5 × TXCLK period)
• RMII: CRS_DV minimum pulse width (1.5 x REFCLK period)
CRS
COL
CRS_DV
807
Figure 12. Asynchronous Input Signal Timing
Min Max Unit
40
—
ns
20
—
ns
35
65
%
14
—
ns
7
—
ns
35
65
%
14
—
ns
7
—
ns
4
—
ns
—
14
ns
Min Max Unit
60
—
ns
30
—
ns
MSC7119 Data Sheet, Rev. 8
30
Freescale Semiconductor