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K61P144M120SF3_1210 Datasheet, PDF (55/87 Pages) Freescale Semiconductor, Inc – K61 Sub-Family | |||
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Peripheral operating requirements and behaviors
6.6.2 CMP and 6-bit DAC electrical specifications
Table 32. Comparator and 6-bit DAC electrical specifications
Symbol
VDD
IDDHS
IDDLS
VAIN
VAIO
VH
Description
Supply voltage
Supply current, High-speed mode (EN=1, PMODE=1)
Supply current, low-speed mode (EN=1, PMODE=0)
Analog input voltage
Analog input offset voltage
Analog comparator hysteresis1
⢠CR0[HYSTCTR] = 00
⢠CR0[HYSTCTR] = 01
⢠CR0[HYSTCTR] = 10
⢠CR0[HYSTCTR] = 11
Min.
1.71
â
â
VSS â 0.3
â
â
â
â
â
Typ.
â
â
â
â
â
5
10
20
30
Max.
3.6
200
20
VDD
20
â
â
â
â
VCMPOh
VCMPOl
tDHS
tDLS
IDAC6b
INL
DNL
Output high
Output low
Propagation delay, high-speed mode (EN=1,
PMODE=1)
Propagation delay, low-speed mode (EN=1,
PMODE=0)
Analog comparator initialization delay2
6-bit DAC current adder (enabled)
6-bit DAC integral non-linearity
6-bit DAC differential non-linearity
VDD â 0.5
â
â
â
â
0.5
20
50
200
80
250
600
â
â
40
â
7
â
â0.5
â
0.5
â0.3
â
0.3
Unit
V
μA
μA
V
mV
mV
mV
mV
mV
V
V
ns
ns
μs
μA
LSB3
LSB
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD-0.6V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN,
VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
K61 Sub-Family Data Sheet, Rev. 4, 10/2012.
Freescale Semiconductor, Inc.
55
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