K61P144M120SF3_1210 Datasheet, PDF (16/87 Pages) Freescale Semiconductor, Inc – K61 Sub-Family

General
5.2.4 Power mode transition operating behaviors
All specifications except t_POR, and VLLSx→RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = FEI 100 MHz
• Bus clock = 50 MHz
• FlexBus clock = 50 MHz
• Flash clock = 25 MHz
Table 5. Power mode transition operating behaviors
Symbol
t_POR
Description
After a POR event, amount of time from the point V_DD
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
• VLLS1 → RUN
Min.
—
—
Max.
300
160
Unit
Notes
μs
1
μs
• VLLS2 → RUN
—
114
μs
• VLLS3 → RUN
—
114
μs
• LLS → RUN
—
5.0
μs
• VLPS → RUN
—
5
μs
• STOP → RUN
—
4.8
μs
1. Normal boot (FTFE_FOPT[LPBOOT]=1)
5.2.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
Symbol
I_DDA
I_{DD_RUN}
Description
Analog supply current
Run mode current — all peripheral clocks
disabled, code executing from flash
• @ 1.8V
• @ 3.0V
Min.
—
Typ.
Max.
Unit
—
See note
mA
—
51.1
160
mA
—
51.7
162
mA
Table continues on the next page...
Notes
1
2
K61 Sub-Family Data Sheet, Rev. 4, 10/2012.
16
Freescale Semiconductor, Inc.