K20P32M50SF0 Datasheet, PDF (55/58 Pages) Freescale Semiconductor, Inc – K20 Sub-Family

Pinout
32 Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
QFN
14 PTA2
JTAG_TDO/ TSI0_CH3 PTA2
TRACE_SWO/
EZP_DO
UART0_TX FTM0_CH7
JTAG_TDO/ EZP_DO
TRACE_SWO
15 PTA3
JTAG_TMS/ TSI0_CH4 PTA3
SWD_DIO
UART0_RTS_b FTM0_CH0
JTAG_TMS/
SWD_DIO
16 PTA4/
LLWU_P3
NMI_b/
EZP_CS_b
TSI0_CH5
PTA4/
LLWU_P3
FTM0_CH1
NMI_b
EZP_CS_b
17 PTA18
EXTAL0
EXTAL0
PTA18
FTM0_FLT2 FTM_CLKIN0
18 PTA19
XTAL0
XTAL0
PTA19
FTM1_FLT0 FTM_CLKIN1
LPTMR0_ALT1
19 RESET_b RESET_b RESET_b
20 PTB0/
LLWU_P5
ADC0_SE8/ ADC0_SE8/ PTB0/
TSI0_CH0 TSI0_CH0 LLWU_P5
I2C0_SCL
FTM1_CH0
FTM1_QD_
PHA
21 PTB1
ADC0_SE9/ ADC0_SE9/ PTB1
TSI0_CH6 TSI0_CH6
I2C0_SDA FTM1_CH1
FTM1_QD_
PHB
22 PTC1/
LLWU_P6
ADC0_SE15/ ADC0_SE15/ PTC1/
TSI0_CH14 TSI0_CH14 LLWU_P6
SPI0_PCS3 UART1_RTS_b FTM0_CH0
I2S0_TXD0
23 PTC2
ADC0_SE4b/ ADC0_SE4b/ PTC2
CMP1_IN0/ CMP1_IN0/
TSI0_CH15 TSI0_CH15
SPI0_PCS2 UART1_CTS_b FTM0_CH1
I2S0_TX_FS
24 PTC3/
LLWU_P7
CMP1_IN1
CMP1_IN1
PTC3/
LLWU_P7
SPI0_PCS1 UART1_RX FTM0_CH2
I2S0_TX_BCLK
25 PTC4/
LLWU_P8
DISABLED
PTC4/
LLWU_P8
SPI0_PCS0 UART1_TX FTM0_CH3
CMP1_OUT
26 PTC5/
LLWU_P9
DISABLED
PTC5/
LLWU_P9
SPI0_SCK
LPTMR0_ALT2 I2S0_RXD0
CMP0_OUT
27 PTC6/
LLWU_P10
CMP0_IN0
CMP0_IN0
PTC6/
LLWU_P10
SPI0_SOUT PDB0_EXTRG I2S0_RX_BCLK
I2S0_MCLK
28 PTC7
CMP0_IN1 CMP0_IN1 PTC7
SPI0_SIN
USB_SOF_ I2S0_RX_FS
OUT
29 PTD4/
LLWU_P14
DISABLED
PTD4/
LLWU_P14
SPI0_PCS1 UART0_RTS_b FTM0_CH4
EWM_IN
30 PTD5
ADC0_SE6b ADC0_SE6b PTD5
SPI0_PCS2
UART0_CTS_ FTM0_CH5
b/
UART0_COL_b
EWM_OUT_b
31 PTD6/
LLWU_P15
ADC0_SE7b ADC0_SE7b PTD6/
LLWU_P15
SPI0_PCS3 UART0_RX
FTM0_CH6
FTM0_FLT0
32 PTD7
DISABLED
PTD7
CMT_IRO UART0_TX FTM0_CH7
FTM0_FLT1
8.2 K20 Pinouts
The below figure shows the pinout diagram for the devices supported by this document.
Many signals may be multiplexed onto a single pin. To determine what signals can be
used on which pin, see the previous section.
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc.
55