K20P32M50SF0 Datasheet, PDF (54/58 Pages) Freescale Semiconductor, Inc – K20 Sub-Family

Dimensions
7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to http://www.freescale.com and perform a keyword
search for the drawing’s document number:
If you want the drawing for this package
32-pin QFN
Then use this document number
98ARE10566D
8 Pinout
8.1 K20 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
32 Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
QFN
1 VDD
VDD
VDD
2 VSS
VSS
VSS
3 USB0_DP USB0_DP USB0_DP
4 USB0_DM USB0_DM USB0_DM
5 VOUT33
VOUT33
VOUT33
6 VREGIN
VREGIN
VREGIN
7 VDDA
VDDA
VDDA
8 VSSA
VSSA
VSSA
9 XTAL32
XTAL32
XTAL32
10 EXTAL32 EXTAL32 EXTAL32
11 VBAT
VBAT
VBAT
12 PTA0
JTAG_TCLK/ TSI0_CH1 PTA0
SWD_CLK/
EZP_CLK
UART0_CTS_ FTM0_CH5
b/
UART0_COL_b
JTAG_TCLK/ EZP_CLK
SWD_CLK
13 PTA1
JTAG_TDI/ TSI0_CH2 PTA1
EZP_DI
UART0_RX FTM0_CH6
JTAG_TDI EZP_DI
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
54
Freescale Semiconductor, Inc.