DSPB56364AF100 Datasheet, PDF (55/148 Pages) Freescale Semiconductor, Inc – 24-Bit Audio Digital Signal Processor

Serial Host Interface SPI Protocol Timing
Table 3-17 Serial Host Interface SPI Protocol Timing (continued)
No.
Characteristics
Mode
Filter
Mode
Expression
Min Max Unit
152 SCK edge to data out valid
(data out delay time)
153 SCK edge to data out not valid
(data out hold time)
154 SS assertion to data out valid
(CPHA = 0)
Master/ Bypassed
Slave
Narrow
Wide
Master/ Bypassed
Slave
Narrow
Wide
Slave
—
2×T_C+33
2×T_C+123
2×T_C+210
T_C+5
T_C+55
T_C+106
T_C+33
—
53
ns
—
143 ns
—
230 ns
15
—
ns
65
—
ns
116
—
ns
—
43
ns
157 First SCK sampling edge to HREQ output
deassertion
Slave Bypassed
Narrow
Wide
158 Last SCK sampling edge to HREQ output not
deasserted (CPHA = 1)
Slave Bypassed
Narrow
Wide
159 SS deassertion to HREQ output not deasserted Slave
—
(CPHA = 0)
2.5×T_C+30
2.5×T_C+120
2.5×T_C+217
2.5×T_C+30
2.5×T_C+80
2.5×T_C+136
2.5×T_C+30
—
55
ns
—
145 ns
—
242 ns
55
—
ns
105
—
ns
161
—
ns
55
—
ns
160 SS deassertion pulse width (CPHA = 0)
161 HREQ in assertion to first SCK edge
162 HREQ in deassertion to last SCK sampling
edge (HREQ in set-up time) (CPHA = 1)
Slave
—
T_C+6
16
—
ns
Master Bypassed 0.5 × t_SPICC +
121
—
ns
2.5×T_C+43
Narrow
0.5 ×t_SPICC +
174
—
ns
2.5×T_C+43
Wide
0.5 ×t_SPICC +
209
—
ns
2.5×T_C+43
Master
—
0
0
—
ns
163 First SCK edge to HREQ in not asserted
(HREQ in hold time)
Note: Periodically sampled, not 100% tested
Master
—
0
0
—
ns
Freescale Semiconductor
DSP56364 Technical Data, Rev. 4.1
3-39