DSPB56364AF100 Datasheet, PDF (30/148 Pages) Freescale Semiconductor, Inc – 24-Bit Audio Digital Signal Processor

External Memory Expansion Port (Port A)
Table 3-8 SRAM Read and Write Accesses¹ (continued)
No.
Characteristics
Symbol
Expression²
Min Max Unit
108 Data valid to WR deassertion (data setup time) t_DS (t_DW) (WS − 0.25) × T_C − 3.0
4.5
—
ns
[WS ≥ 1]
109 Data hold time from WR deassertion
t_DH
0.25 × T_C − 2.0
0.5
—
ns
[1 ≤ WS ≤ 3]
1.25 × T_C − 2.0
[4 ≤ WS ≤ 7]
10.5 —
ns
2.25 × T_C − 2.0
[WS ≥ 8]
20.5 —
ns
113 RD deassertion time
0.75 × T_C − 4.0
[1 ≤ WS ≤ 3]
3.5
—
ns
1.75 × T_C − 4.0
[4 ≤ WS ≤ 7]
13.5 —
ns
2.75 × T_C − 4.0
[WS ≥ 8]
23.5 —
ns
114 WR deassertion time
0.5 × T_C − 4.0
[WS = 1]
1.0
—
ns
T_C − 2.0
[2 ≤ WS ≤ 3]
6.0
—
ns
2.5 × T_C − 4.0
[4 ≤ WS ≤ 7]
21.0 —
ns
3.5 × T_C − 4.0
[WS ≥ 8]
31.0 —
ns
115 Address valid to RD assertion
116 RD assertion pulse width
117 RD deassertion to address not valid
0.5 × T_C − 4.0
1.0
—
ns
(WS + 0.25) × T_C −4.0
8.5
—
ns
0.25 × T_C − 2.0
[1 ≤ WS ≤ 3]
0.5
—
ns
1.25 × T_C − 2.0
[4 ≤ WS ≤ 7]
10.5 —
ns
2.25 × T_C − 2.0
[WS ≥ 8]
20.5 —
ns
3-14
DSP56364 Technical Data, Rev. 4.1
Freescale Semiconductor