DSPB56364AF100 Datasheet, PDF (49/148 Pages) Freescale Semiconductor, Inc – 24-Bit Audio Digital Signal Processor

External Memory Expansion Port (Port A)
Table 3-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States^{1, 2} (continued)
No.
Characteristics³
Symbol
Expression⁴
Min Max Unit
191 RD assertion to RAS deassertion
t_ROH
11.5 × T_C − 4.0 111.0 —
ns
192 RD assertion to data valid
193 RD deassertion to data not valid³
t_GA
10 × T_C − 7.0
— 93.0 ns
t_GZ
0.0
—
ns
194 WR assertion to data active
0.75 × T_C − 0.3
7.2
—
ns
195 WR deassertion to data high impedance
0.25 × T_C
—
2.5
ns
1 _{The number of wait states for out-of-page access is specified in the DCR.}
2 _{The refresh period is specified in the DCR.}
3 _{RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ.}
4 _{The asynchronous delays specified in the expressions are valid for DSP56364.}
5 _{Either tRCH or tRRH must be satisfied for read cycles.}
Table 3-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States^{1, 2}
No.
Characteristics³
Symbol
Expression
Min Max Unit
157 Random read or write cycle time
158 RAS assertion to data valid (read)
159 CAS assertion to data valid (read)
160 Column address valid to data valid (read)
161 CAS deassertion to data not valid (read hold time)
162 RAS deassertion to RAS assertion
163 RAS assertion pulse width
164 CAS assertion to RAS deassertion
165 RAS assertion to CAS deassertion
166 CAS assertion pulse width
167 RAS assertion to CAS assertion
168 RAS assertion to column address valid
169 CAS deassertion to RAS assertion
170 CAS deassertion pulse width
171 Row address valid to RAS assertion
172 RAS assertion to row address not valid
t_RC
t_RAC
t_CAC
t_AA
t_OFF
t_RP
t_RAS
t_RSH
t_CSH
t_CAS
t_RCD
t_RAD
t_CRP
t_CP
t_ASR
t_RAH
16 × T_C
8.25 × T_C − 5.7
4.75 × T_C − 5.7
5.5 × T_C − 5.7
0.0
6.25 × T_C − 4.0
9.75 × T_C − 4.0
6.25 × T_C − 4.0
8.25 × T_C − 4.0
4.75 × T_C − 4.0
3.5 × T_C ± 2
2.75 × T_C ± 2
7.75 × T_C − 4.0
6.25 × T_C − 4.0
6.25 × T_C − 4.0
2.75 × T_C − 4.0
160.0 —
ns
— 76.8 ns
— 41.8 ns
— 49.3 ns
0.0
—
ns
58.5
—
ns
93.5
—
ns
58.5
—
ns
78.5
—
ns
43.5
—
ns
33.0 37.0 ns
25.5 29.5 ns
73.5
—
ns
58.5
—
ns
58.5
—
ns
23.5
—
ns
Freescale Semiconductor
DSP56364 Technical Data, Rev. 4.1
3-33