K22P121M50SF4 Datasheet, PDF (51/61 Pages) Freescale Semiconductor, Inc – K22 Sub-Family Data Sheet

Num.
S11
S12
S13
S14
S15
S16
S17
S18
S19
Peripheral operating requirements and behaviors
Table 40. I2S/SAI slave mode timing
Characteristic
Operating voltage
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
I2S_RXD setup before I2S_RX_BCLK
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid¹
Min.
1.71
80
45%
10
2
—
0
10
2
—
Max.
3.6
—
55%
—
—
29
—
—
—
21
Unit
V
ns
MCLK period
ns
ns
ns
ns
ns
ns
ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
I2S_TX_BCLK/
I2S_RX_BCLK (input)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TX_FS/
I2S_RX_FS (input)
I2S_TXD
I2S_RXD
S11
S12
S15
S13
S19
S15
S12
S15
S16
S17
S18
S16
S14
S16
Figure 21. I2S/SAI timing — slave modes
6.8.9 VLPR, VLPW, and VLPS mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in VLPR, VLPW, and VLPS modes.
K22 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012.
Freescale Semiconductor, Inc.
51