MC68882EI25A Datasheet, PDF (5/26 Pages) Freescale Semiconductor, Inc – HCMOS Enhanced Floating-Point Coprocessor

Freescale Semiconductor, Inc.
(BIU), the conversion unit (CU), and the arithmetic proc-
cycle. (The function codes are generated by the M68000
essing unit (APU). The BIU communicates with the
Family processors to identify eight separate address
MC68620 or MC68030, the CU performs data conversion
spaces.)” Thus, the memory-mapped coprocessor inter-
For binary real data formats, and the APU executes all
face registers do not infringe upon instruction or data
MC68882 instructions.
address spaces. The MC68020 or MC68030 places a co-
The BIU contains the coprocessor interface registers
processor ID field from the coprocessor instruction onto
(CIRS). In addition to these registers, the register select
three of the upper address lines during coprocessor ac-
and DSACK timing control logic is contained in the BIU.
cesses. This ID, along with the CPU address space func-
Finally, the status flags used to monitor the status of
tion code, is decoded to select one of eight coprocessor
communications with the main processor are contained
in the system.
~~~~.~l,
in the BIU.
Since the coprocessor interface protocol is ba~~wlely
The CU contains special purpose hardware that per-
on bus transfers, the protocol is easily ernu~?~q~~y soft-
forms data format conversions between binary real data
ware when the MC68882 is used as a perl,~~:~~ktiith any
formats to and from ‘the internal extended format. The
processor capable of memory-mapped @+@yaTan M68000
CU relieves the APU of a significant work load and allows
style bus. When used as a periphe$$.@r@ssor with the
the MC68882 to execute data movement and preparation
8-bit MC68008, the 16-bit MC68,R{:~$r?he .MC68010, all
functions concurrently with arithmetic and transcenden-
MC68882 instructions are trapp~$:$ the main processor
tal calculations,
to an exception handler at g$$cut?~n time. Thus, the soft-
The eight 80-bit floating-point data registers (FPO-FP7)
ware emulation of the c~~~~~$~or interface protocol can
and the 32-bit control, status, and instruction address
be totally transparent%~~:t~&Wser. The MC68882 can pre-
registers (FPCR, FPSR and FPIAR) are located in the APU.
vide a performancetW~~.@ for MC68000-based designs
In addition to these registers, the APU contains a high-
by changing the ‘T~%~@’*processors to the MC68020 or
speed 67-bit arithmetic unit used for both mantissa and
MC68030. Th,~~pftMre migrates without change to the
exponent calculations, a barrel shifter that can shift from
next gener&k$&#$eq uipment using the MC68020 or
1 bit to 67 bits in one machine cycle, and ROM constants
MC6803@s”’:?JW’
(for use by the internal algorithms or user programs).
Sin@’J%&$s is asynchronous, the MC68882 need not
The control section of the APU contains the clock gen-
ru~.at~g same clock speed as the main processor. Total
erator, a two-level microcode sequencer, the microcode
,J,~$&~~mperformance may therefore be customized. For a
ROM, and self-test circuitry. The built-in self-test capa- : Weti CPU performance requirement, the floating-point
bilities of the MC68882 enhance reliability and ease man- S+~&.$@’iformance can be selected to meet Particular Price/
ufacturing requirements; however, these diagnost~~~%k~ performance specifications, running the MC68882 at
functions are not accessible outside of the special test ‘t slower (or faster) clock speeds than the MPU clock.
All communications
,, s~i;,y+,.>~.
between the MC68@~~OFWC68030
and the MC68882 occur via standard M@~~Q:@>amily bus
transfers, The MC68882 is design,~t~~~~~erate
16-, or 32-bit data buses.
p?:f}>,\~, ^{.$*.i7\y\~.<, :..}
The MC68882 contains a nu@b#~.~coprocessor
on 8-,
inter-
face registers (CIRS) that ar~.~~r$ised in the same man-
ner as memory by the rnai~~~~essor. The M68000 Family
coprocessor interface.r$<!#~@emented via a protocol of
reading and writing t$$~#se registers by the main pro-
cessor. The MC6~@‘’.:!:,$~~0~ _..a+nfl MC68030 implement this gen-
eral purpose co~ra$~ssor interface protocol in hardware
and microc~$~,$~~~ ~
WhenJh*~$~&68020 or MC68030 detects a general type
MC68&Q~~~s?tuction, the MC68020 or MC68030 writes
the,i@tru$~on to the memory-mapped command CIR and
r~‘+S’.:&:t.:%.~l’~:~&’.rte~s.ponse CIR. In this response, the BIU encodes
~i%{e$~ests for any additional action required of the MC68020
“$.@~C68030 on behalf of the MC68882. For example, the
‘%sponse may request that the MC68020 or MC68030 fetch
an operand from the evaluated effective address and
transfer the operand to the operand CIR. Once the
MC68020 or MC68030 fulfills the coprocessor request(s),
the MC68020 or MC68030 is free to fetch and execute
subsequent instructions.
The only difference between a coprocessor bus transfer
and any other bus transfer is that the MC68020 or MC68030
issues a CPU address space function code during the
COPROCESSOR INTERFACE
The M68000 Family coprocessor interface is an integral
part of the MC68882 and MC68020 or MC68030 designs.
The interface partitions MPU and coprocessor operations
so that the MC68020 or MC68030 does not have to corn-
pletely decode coprocessor instructions, and the MC68882
does not have to duplicate main processor functions (such
as effective address evaluation). This partitioning pro-
vides an orthogonal extension of the instruction set by
permitting MC68882 instructions to utilize all MC68020
or MC68030 addressing modes and to generate execution
time exception traps. Thus, from the programmer’s view,
the MPU and coprocessor appear to be integrated onto
a single chip.
While the execution of the great majority of MC68882
instructions may be overlapped with the execution of
MC68020 or MC68030 instructions, concurrency is com-
pletelytransparent to the programmer. The MC68020 and
MC68030 single-step and program flow (trace) modes are
fully supported by the MC68882 and the M68000 Family
coprocessor interface.
While the M68000 Family coprocessor interface per-
mits coprocessor to be bus masters, the MC68882 is
never a bus master. The MC68882 requests that the
MC68020 or MC68030 fetch all operands and store all
results. In this manner, the MC68020 and MC68030 32-
bit data bus provides high speed transfer of floating-point
operands and results while simplifying the design of the
MC68882.
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