MCIMX31C_10 Datasheet, PDF (48/108 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processors for Industrial and Automotive Products

Electrical Characteristics
SDCLK
SDCLK
DQS (input)
DQ (input)
SD23
SD21
Data
SD22
Data
Data
Data
Data
Data
Data
Data
Figure 38. Mobile DDR SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram
Table 36. Mobile DDR SDRAM Read Cycle Timing Parameters
ID
Parameter
SD21 DQS – DQ Skew (defines the Data valid window in read cycles related to DQS).
SD22 DQS DQ HOLD time from DQS
SD23 DQS output access time from SDCLK posedge
Symbol Min Max Unit
tDQSQ — 0.85 ns
tQH 2.3 — ns
tDQSCK — 6.7 ns
NOTE
SDRAM CLK and DQS related parameters are being measured from the
50% point—that is, high is defined as 50% of signal value and low is
defined as 50% of signal value.
NOTE
The timing parameters are similar to the ones used in SDRAM data
sheets—that is, Table 36 indicates SDRAM requirements. All output signals
are driven by the ESDCTL at the negative edge of SDCLK and the
parameters are measured at maximum memory frequency.
4.3.10 ETM Electrical Specifications
ETM is an ARM protocol. The timing specifications in this section are given as a guide for a TPA that
supports TRACECLK frequencies up to 133 MHz.
Figure 39 depicts the TRACECLK timings of ETM, and Table 37 lists the timing parameters.
Figure 39. ETM TRACECLK Timing Diagram
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
48
Freescale Semiconductor