MCIMX31C_10 Datasheet, PDF (21/108 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processors for Industrial and Automotive Products

Electrical Characteristics
Table 19. WR0 Sequence Timing Parameters
ID
OW5
OW6
Parameter
Write 0 Low Time
Transmission Time Slot
Symbol
t_{WR0_low}
t_SLOT
Min
60
OW5
Typ
Max
Units
100
120
µs
117
120
µs
Figure 8 depicts Write 1 Sequence timing, Figure 9 depicts the Read Sequence timing, and Table 20 lists
the timing parameters.
1-Wire bus
(BATT_LINE)
OW8
1-Wire bus
(BATT_LINE)
OW7
Figure 8. Write 1 Sequence Timing Diagram
OW8
ID
OW7
OW8
OW9
OW7
OW9
Figure 9. Read Sequence Timing Diagram
Table 20. WR1/RD Timing Parameters
Parameter
Write 1 / Read Low Time
Transmission Time Slot
Release Time
Symbol
Min
Typ
t_LOW1
1
5
t_SLOT
60
117
t_RELEASE
15
—
Max
Units
15
µs
120
µs
45
µs
4.3.5 ATA Electrical Specifications (ATA Bus, Bus Buffers)
This section discusses ATA parameters. For a detailed description, refer to the ATA specification.
The user needs to use level shifters for 3.3 Volt or 5.0 Volt compatibility on the ATA interface.
The use of bus buffers introduces delay on the bus and introduces skew between signal lines. These factors
make it difficult to operate the bus at the highest speed (UDMA-5) when bus buffers are used. If fast
UDMA mode operation is needed, this may not be compatible with bus buffers.
Another area of attention is the slew rate limit imposed by the ATA specification on the ATA bus.
According to this limit, any signal driven on the bus should have a slew rate between 0.4 and 1.2 V/ns with
a 40 pF load. Not many vendors of bus buffers specify slew rate of the outgoing signals.
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
Freescale Semiconductor
21