K30P144M100SF2 Datasheet, PDF (46/67 Pages) Freescale Semiconductor, Inc – K30 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
Table 28. 12-bit DAC operating requirements (continued)
Symbol
C_L
I_L
Desciption
Output load capacitance
Output load current
Min.
Max.
Unit
—
100
pF
—
1
mA
1. The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREFO)
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC
Notes
2
6.6.3.2 12-bit DAC operating behaviors
Table 29. 12-bit DAC operating behaviors
Symbol Description
n
Resolution
y _{IDDA_DACLP Supply current — low-power mode}
r _{IDDA_DACH Supply current — high-speed mode}
P
a tDACLP Full-scale settling time (0x080 to 0xF7F) — low-
power mode
in tDACHP Full-scale settling time (0x080 to 0xF7F) — high-
power mode
t_CCDACLP Code-to-code settling time (0xBF8 to 0xC08) —
low-power mode
t_CCDACHP Code-to-code settling time (0xBF8 to 0xC08) —
lim ^{high-speed mode}
V_dacoutl DAC output voltage range low — high-speed
mode, no load, DAC set to 0x000
V_dacouth DAC output voltage range high — high-speed
e ^{mode, no load, DAC set to 0xFFF}
INL Integral non-linearity error — high speed mode
r _DNL
P ^DNL
Differential non-linearity error — V_DACR > 2 V
Differential non-linearity error — V_DACR = VRE‐
Min.
12
—
—
—
—
—
1
0
V_DACR
−100
±3
±0.5
±0.5
Typ.
—
—
—
100
15
—
TBD
100
—
—
—
—
Max.
12
150
700
200
30
5
—
—
V_DACR
±8
±1
±1
Unit
b
μA
μA
μs
μs
μs
μs
mV
mV
LSB
LSB
LSB
FO (1.15 V)
V_OFFSET
E_G
PSRR
T_CO
T_GE
Offset error
Gain error
Power supply rejection ratio, V_DDA > = 2.4 V
Temperature coefficient offset voltage
Temperature coefficient gain error
±0.4
—
±0.8
%FSR
±0.1
—
±0.6
%FSR
60
90
dB
—
TBD
—
μV/C
—
TBD
—
ppm of
FSR/C
A_C
Offset aging coefficient
Rop Output resistance load = 3 kΩ
—
—
TBD
μV/yr
—
—
250
Ω
Table continues on the next page...
Notes
1
1
1
1
2
3
4
5
5
K30 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
46
Preliminary
Freescale Semiconductor, Inc.